Re: [RFC PATCH v4 04/22] target/arm: Implement ALLINT MSR (immediate)

[Richard Henderson]

On 2/27/24 23:29, Jinjie Ruan via wrote:
> Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The
> EL0 check is necessary to ALLINT, and the EL1 check is necessary when
> imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the
> unconditional write to pc and use raise_exception_ra to unwind.
>
> Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
> ---
> v4:
> - Fix the ALLINT MSR (immediate) decodetree implementation.
> - Remove arm_is_el2_enabled() check in allint_check().
> - Update env->allint to env->pstate.
> - Only call allint_check() when imm == 1.
> - Simplify the allint_check() to not pass "op" and extract.
> - Implement it inline for EL2/3, or EL1 with imm==0.
> - Pass (a->imm & 1) * PSTATE_ALLINT (i64) to simplfy the ALLINT set/clear.
> v3:
> - Remove EL0 check in allint_check().
> - Add TALLINT check for EL1 in allint_check().
> - Remove unnecessarily arm_rebuild_hflags() in msr_i_allint helper.
> ---
>   target/arm/tcg/a64.decode      |  1 +
>   target/arm/tcg/helper-a64.c    | 16 ++++++++++++++++
>   target/arm/tcg/helper-a64.h    |  1 +
>   target/arm/tcg/translate-a64.c | 19 +++++++++++++++++++
>   4 files changed, 37 insertions(+)
>
> diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
> index 8a20dce3c8..0e7656fd15 100644
> --- a/target/arm/tcg/a64.decode
> +++ b/target/arm/tcg/a64.decode
> @@ -207,6 +207,7 @@ MSR_i_DIT       1101 0101 0000 0 011 0100 .... 010 11111 
> @msr_i
>   MSR_i_TCO       1101 0101 0000 0 011 0100 .... 100 11111 @msr_i
>   MSR_i_DAIFSET   1101 0101 0000 0 011 0100 .... 110 11111 @msr_i
>   MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i
> +MSR_i_ALLINT    1101 0101 0000 0 001 0100 000 imm:1 000 11111

Good.

> +static void allint_check(CPUARMState *env, uintptr_t ra)
> +{
> +    /* ALLINT update to PSTATE. */
> +    if (arm_current_el(env) == 1 && (arm_hcrx_el2_eff(env) & HCRX_TALLINT)) {

You know this will only be called for EL1.
Since the function is only used once, might as well merge...

> +        raise_exception_ra(env, EXCP_UDEF,
> +                           syn_aa64_sysregtrap(0, 1, 0, 4, 1, 0x1f, 0),
> +                           exception_target_el(env), ra);
> +    }
> +}
> +
> +void HELPER(msr_i_allint)(CPUARMState *env, uint64_t val)
> +{
> +    allint_check(env, GETPC());

... with the only caller.

> +    env->pstate = (env->pstate & ~PSTATE_ALLINT) | (val & PSTATE_ALLINT);

You know that val always equals PSTATE_ALLINT, so this simplifies to

    env->pstate |= PSTATE_ALLINT;

I suggest a rename to msr_set_allint_el1.

> +static bool trans_MSR_i_ALLINT(DisasContext *s, arg_i *a)
> +{
> +    if (!dc_isar_feature(aa64_nmi, s) || s->current_el == 0) {
> +        return false;
> +    }
> +
> +    if ((a->imm & 1) == 0) {

imm is only one bit, per decode, so you can drop the & 1 here.

> +        clear_pstate_bits(PSTATE_ALLINT);
> +    } else if (s->current_el > 1) {
> +        set_pstate_bits(PSTATE_ALLINT);
> +    } else {
> +        gen_helper_msr_i_allint(tcg_env,
> +                                tcg_constant_tl((a->imm & 1) * PSTATE_ALLINT));

Because you've already eliminated imm == 0, you know imm is always 1, so that simplifies 
the entire function definition, per above.


r~