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[RFC PATCH v4 08/22] target/arm: Handle IS/FS in ISR_EL1 for NMI
From: |
Jinjie Ruan |
Subject: |
[RFC PATCH v4 08/22] target/arm: Handle IS/FS in ISR_EL1 for NMI |
Date: |
Wed, 28 Feb 2024 09:29:32 +0000 |
Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or
CPU_INTERRUPT_VNMI, both CPSR_I and ISR_IS must be set. With
CPU_INTERRUPT_VFIQ and HCRX_EL2.VFNMI set, both CPSR_F and ISR_FS must be set.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
---
v4;
- Also handle VNMI.
v3:
- CPU_INTERRUPT_NMI do not set FIQ, so remove it.
- With CPU_INTERRUPT_NMI, both CPSR_I and ISR_IS must be set.
---
target/arm/cpu.h | 2 ++
target/arm/helper.c | 13 +++++++++++++
2 files changed, 15 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 8be978698d..22f0763e66 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1475,6 +1475,8 @@ FIELD(CPTR_EL3, TCPAC, 31, 1)
#define CPSR_N (1U << 31)
#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
+#define ISR_FS (1U << 9)
+#define ISR_IS (1U << 10)
#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7cdc90e9e3..ac44498537 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2018,15 +2018,28 @@ static uint64_t isr_read(CPUARMState *env, const
ARMCPRegInfo *ri)
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
ret |= CPSR_I;
}
+ if (cs->interrupt_request & CPU_INTERRUPT_VNMI) {
+ ret |= ISR_IS;
+ ret |= CPSR_I;
+ }
} else {
if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
ret |= CPSR_I;
}
+
+ if (cs->interrupt_request & CPU_INTERRUPT_NMI) {
+ ret |= ISR_IS;
+ ret |= CPSR_I;
+ }
}
if (hcr_el2 & HCR_FMO) {
if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
ret |= CPSR_F;
+
+ if (env->cp15.hcrx_el2 & HCRX_VFNMI) {
+ ret |= ISR_FS;
+ }
}
} else {
if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
--
2.34.1
- [RFC PATCH v4 18/22] hw/intc/arm_gicv3: Implement NMI interrupt prioirty, (continued)
- [RFC PATCH v4 18/22] hw/intc/arm_gicv3: Implement NMI interrupt prioirty, Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 12/22] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64(), Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 16/22] hw/intc: Enable FEAT_GICv3_NMI Feature, Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 06/22] target/arm: Add support for Non-maskable Interrupt, Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 21/22] target/arm: Add FEAT_NMI to max, Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 11/22] hw/intc/arm_gicv3: Add external IRQ lines for NMI, Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 04/22] target/arm: Implement ALLINT MSR (immediate), Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 05/22] target/arm: Support MSR access to ALLINT, Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 14/22] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0, Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 19/22] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update(), Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 08/22] target/arm: Handle IS/FS in ISR_EL1 for NMI,
Jinjie Ruan <=
- [RFC PATCH v4 03/22] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt, Jinjie Ruan, 2024/02/28
- [RFC PATCH v4 10/22] hw/arm/virt: Wire NMI and VNMI irq lines from GIC to CPU, Jinjie Ruan, 2024/02/28