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[PULL 19/61] target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[]
From: |
Alistair Francis |
Subject: |
[PULL 19/61] target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[] |
Date: |
Fri, 9 Feb 2024 20:57:31 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Keep all class properties in riscv_cpu_properties[].
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
tested-by tags added, rebased with Alistair's riscv-to-apply.next.
Message-ID: <20240112140201.127083-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 68 ++++++++++++++++++++++++----------------------
1 file changed, 36 insertions(+), 32 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a14d7da11d..1a6524f01f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2020,6 +2020,41 @@ static const PropertyInfo prop_mvendorid = {
.set = prop_mvendorid_set,
};
+static void prop_mimpid_set(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ uint64_t prev_val = cpu->cfg.mimpid;
+ uint64_t value;
+
+ if (!visit_type_uint64(v, name, &value, errp)) {
+ return;
+ }
+
+ if (!dynamic_cpu && prev_val != value) {
+ error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")",
+ object_get_typename(obj), prev_val);
+ return;
+ }
+
+ cpu->cfg.mimpid = value;
+}
+
+static void prop_mimpid_get(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ uint64_t value = RISCV_CPU(obj)->cfg.mimpid;
+
+ visit_type_uint64(v, name, &value, errp);
+}
+
+static const PropertyInfo prop_mimpid = {
+ .name = "mimpid",
+ .get = prop_mimpid_get,
+ .set = prop_mimpid_set,
+};
+
/*
* RVA22U64 defines some 'named features' or 'synthetic extensions'
* that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa
@@ -2107,6 +2142,7 @@ static Property riscv_cpu_properties[] = {
{.name = "cboz_blocksize", .info = &prop_cboz_blksize},
{.name = "mvendorid", .info = &prop_mvendorid},
+ {.name = "mimpid", .info = &prop_mimpid},
#ifndef CONFIG_USER_ONLY
DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
@@ -2188,35 +2224,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
};
#endif
-static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
- RISCVCPU *cpu = RISCV_CPU(obj);
- uint64_t prev_val = cpu->cfg.mimpid;
- uint64_t value;
-
- if (!visit_type_uint64(v, name, &value, errp)) {
- return;
- }
-
- if (!dynamic_cpu && prev_val != value) {
- error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")",
- object_get_typename(obj), prev_val);
- return;
- }
-
- cpu->cfg.mimpid = value;
-}
-
-static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- uint64_t value = RISCV_CPU(obj)->cfg.mimpid;
-
- visit_type_uint64(v, name, &value, errp);
-}
-
static void cpu_set_marchid(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
@@ -2298,9 +2305,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void
*data)
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
- object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid,
- cpu_set_mimpid, NULL, NULL);
-
object_class_property_add(c, "marchid", "uint64", cpu_get_marchid,
cpu_set_marchid, NULL, NULL);
--
2.43.0
- [PULL 09/61] target/riscv: rework 'priv_spec', (continued)
- [PULL 09/61] target/riscv: rework 'priv_spec', Alistair Francis, 2024/02/09
- [PULL 10/61] target/riscv: rework 'vext_spec', Alistair Francis, 2024/02/09
- [PULL 11/61] target/riscv: move 'vlen' to riscv_cpu_properties[], Alistair Francis, 2024/02/09
- [PULL 12/61] target/riscv: move 'elen' to riscv_cpu_properties[], Alistair Francis, 2024/02/09
- [PULL 14/61] target/riscv: move 'cbom_blocksize' to riscv_cpu_properties[], Alistair Francis, 2024/02/09
- [PULL 13/61] target/riscv: create finalize_features() for KVM, Alistair Francis, 2024/02/09
- [PULL 15/61] target/riscv: move 'cbop_blocksize' to riscv_cpu_properties[], Alistair Francis, 2024/02/09
- [PULL 16/61] target/riscv: move 'cboz_blocksize' to riscv_cpu_properties[], Alistair Francis, 2024/02/09
- [PULL 17/61] target/riscv: remove riscv_cpu_options[], Alistair Francis, 2024/02/09
- [PULL 18/61] target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[], Alistair Francis, 2024/02/09
- [PULL 19/61] target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[],
Alistair Francis <=
- [PULL 20/61] target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[], Alistair Francis, 2024/02/09
- [PULL 21/61] target/riscv: Implement optional CSR mcontext of debug Sdtrig extension, Alistair Francis, 2024/02/09
- [PULL 22/61] target/riscv: add 'vlenb' field in cpu->cfg, Alistair Francis, 2024/02/09
- [PULL 23/61] target/riscv/csr.c: use 'vlenb' instead of 'vlen', Alistair Francis, 2024/02/09
- [PULL 25/61] target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb, Alistair Francis, 2024/02/09
- [PULL 24/61] target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen', Alistair Francis, 2024/02/09
- [PULL 26/61] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb', Alistair Francis, 2024/02/09
- [PULL 27/61] target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb', Alistair Francis, 2024/02/09
- [PULL 28/61] target/riscv/vector_helper.c: use 'vlenb', Alistair Francis, 2024/02/09
- [PULL 29/61] target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl), Alistair Francis, 2024/02/09