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[PATCH v5 09/20] i386: Decouple CPUID[0x1F] subleaf with specific topolo
From: |
Zhao Liu |
Subject: |
[PATCH v5 09/20] i386: Decouple CPUID[0x1F] subleaf with specific topology level |
Date: |
Tue, 24 Oct 2023 17:03:12 +0800 |
From: Zhao Liu <zhao1.liu@intel.com>
At present, the subleaf 0x02 of CPUID[0x1F] is bound to the "die" level.
In fact, the specific topology level exposed in 0x1F depends on the
platform's support for extension levels (module, tile and die).
To help expose "module" level in 0x1F, decouple CPUID[0x1F] subleaf
with specific topology level.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Babu Moger <babu.moger@amd.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
---
Changes since v3:
* New patch to prepare to expose module level in 0x1F.
* Move the CPUTopoLevel enumeration definition from "i386: Add cache
topology info in CPUCacheInfo" to this patch. Note, to align with
topology types in SDM, revert the name of CPU_TOPO_LEVEL_UNKNOW to
CPU_TOPO_LEVEL_INVALID.
---
target/i386/cpu.c | 136 +++++++++++++++++++++++++++++++++++++---------
target/i386/cpu.h | 15 +++++
2 files changed, 126 insertions(+), 25 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ed65b7b8cf76..1de18b98ca29 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -269,6 +269,116 @@ static void encode_cache_cpuid4(CPUCacheInfo *cache,
(cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
}
+static uint32_t num_cpus_by_topo_level(X86CPUTopoInfo *topo_info,
+ enum CPUTopoLevel topo_level)
+{
+ switch (topo_level) {
+ case CPU_TOPO_LEVEL_SMT:
+ return 1;
+ case CPU_TOPO_LEVEL_CORE:
+ return topo_info->threads_per_core;
+ case CPU_TOPO_LEVEL_DIE:
+ return topo_info->threads_per_core * topo_info->cores_per_die;
+ case CPU_TOPO_LEVEL_PACKAGE:
+ return topo_info->threads_per_core * topo_info->cores_per_die *
+ topo_info->dies_per_pkg;
+ default:
+ g_assert_not_reached();
+ }
+ return 0;
+}
+
+static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info,
+ enum CPUTopoLevel topo_level)
+{
+ switch (topo_level) {
+ case CPU_TOPO_LEVEL_SMT:
+ return 0;
+ case CPU_TOPO_LEVEL_CORE:
+ return apicid_core_offset(topo_info);
+ case CPU_TOPO_LEVEL_DIE:
+ return apicid_die_offset(topo_info);
+ case CPU_TOPO_LEVEL_PACKAGE:
+ return apicid_pkg_offset(topo_info);
+ default:
+ g_assert_not_reached();
+ }
+ return 0;
+}
+
+static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level)
+{
+ switch (topo_level) {
+ case CPU_TOPO_LEVEL_INVALID:
+ return CPUID_1F_ECX_TOPO_LEVEL_INVALID;
+ case CPU_TOPO_LEVEL_SMT:
+ return CPUID_1F_ECX_TOPO_LEVEL_SMT;
+ case CPU_TOPO_LEVEL_CORE:
+ return CPUID_1F_ECX_TOPO_LEVEL_CORE;
+ case CPU_TOPO_LEVEL_DIE:
+ return CPUID_1F_ECX_TOPO_LEVEL_DIE;
+ default:
+ /* Other types are not supported in QEMU. */
+ g_assert_not_reached();
+ }
+ return 0;
+}
+
+static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count,
+ X86CPUTopoInfo *topo_info,
+ uint32_t *eax, uint32_t *ebx,
+ uint32_t *ecx, uint32_t *edx)
+{
+ static DECLARE_BITMAP(topo_bitmap, CPU_TOPO_LEVEL_MAX);
+ X86CPU *cpu = env_archcpu(env);
+ unsigned long level, next_level;
+ uint32_t num_cpus_next_level, offset_next_level;
+
+ /*
+ * Initialize the bitmap to decide which levels should be
+ * encoded in 0x1f.
+ */
+ if (!count) {
+ /* SMT and core levels are exposed in 0x1f leaf by default. */
+ set_bit(CPU_TOPO_LEVEL_SMT, topo_bitmap);
+ set_bit(CPU_TOPO_LEVEL_CORE, topo_bitmap);
+
+ if (env->nr_dies > 1) {
+ set_bit(CPU_TOPO_LEVEL_DIE, topo_bitmap);
+ }
+ }
+
+ *ecx = count & 0xff;
+ *edx = cpu->apic_id;
+
+ level = find_first_bit(topo_bitmap, CPU_TOPO_LEVEL_MAX);
+ if (level == CPU_TOPO_LEVEL_MAX) {
+ num_cpus_next_level = 0;
+ offset_next_level = 0;
+
+ /* Encode CPU_TOPO_LEVEL_INVALID into the last subleaf of 0x1f. */
+ level = CPU_TOPO_LEVEL_INVALID;
+ } else {
+ next_level = find_next_bit(topo_bitmap, CPU_TOPO_LEVEL_MAX, level + 1);
+ if (next_level == CPU_TOPO_LEVEL_MAX) {
+ next_level = CPU_TOPO_LEVEL_PACKAGE;
+ }
+
+ num_cpus_next_level = num_cpus_by_topo_level(topo_info, next_level);
+ offset_next_level = apicid_offset_by_topo_level(topo_info, next_level);
+ }
+
+ *eax = offset_next_level;
+ *ebx = num_cpus_next_level;
+ *ecx |= cpuid1f_topo_type(level) << 8;
+
+ assert(!(*eax & ~0x1f));
+ *ebx &= 0xffff; /* The count doesn't need to be reliable. */
+ if (level != CPU_TOPO_LEVEL_MAX) {
+ clear_bit(level, topo_bitmap);
+ }
+}
+
/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
{
@@ -6283,31 +6393,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
break;
}
- *ecx = count & 0xff;
- *edx = cpu->apic_id;
- switch (count) {
- case 0:
- *eax = apicid_core_offset(&topo_info);
- *ebx = topo_info.threads_per_core;
- *ecx |= CPUID_1F_ECX_TOPO_LEVEL_SMT << 8;
- break;
- case 1:
- *eax = apicid_die_offset(&topo_info);
- *ebx = topo_info.cores_per_die * topo_info.threads_per_core;
- *ecx |= CPUID_1F_ECX_TOPO_LEVEL_CORE << 8;
- break;
- case 2:
- *eax = apicid_pkg_offset(&topo_info);
- *ebx = cpus_per_pkg;
- *ecx |= CPUID_1F_ECX_TOPO_LEVEL_DIE << 8;
- break;
- default:
- *eax = 0;
- *ebx = 0;
- *ecx |= CPUID_1F_ECX_TOPO_LEVEL_INVALID << 8;
- }
- assert(!(*eax & ~0x1f));
- *ebx &= 0xffff; /* The count doesn't need to be reliable. */
+ encode_topo_cpuid1f(env, count, &topo_info, eax, ebx, ecx, edx);
break;
case 0xD: {
/* Processor Extended State */
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index f6dff5f372bc..e21bb20405af 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1008,6 +1008,21 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord
w,
#define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */
#define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
+/*
+ * CPUTopoLevel is the general i386 topology hierarchical representation,
+ * ordered by increasing hierarchical relationship.
+ * Its enumeration value is not bound to the type value of Intel (CPUID[0x1F])
+ * or AMD (CPUID[0x80000026]).
+ */
+enum CPUTopoLevel {
+ CPU_TOPO_LEVEL_INVALID,
+ CPU_TOPO_LEVEL_SMT,
+ CPU_TOPO_LEVEL_CORE,
+ CPU_TOPO_LEVEL_DIE,
+ CPU_TOPO_LEVEL_PACKAGE,
+ CPU_TOPO_LEVEL_MAX,
+};
+
/* CPUID[0xB].ECX level types */
#define CPUID_B_ECX_TOPO_LEVEL_INVALID 0
#define CPUID_B_ECX_TOPO_LEVEL_SMT 1
--
2.34.1
- [PATCH v5 00/20] Support smp.clusters for x86 in QEMU, Zhao Liu, 2023/10/24
- [PATCH v5 01/20] i386: Fix comment style in topology.h, Zhao Liu, 2023/10/24
- [PATCH v5 02/20] tests: Rename test-x86-cpuid.c to test-x86-topo.c, Zhao Liu, 2023/10/24
- [PATCH v5 03/20] softmmu: Fix CPUSTATE.nr_cores' calculation, Zhao Liu, 2023/10/24
- [PATCH v5 04/20] hw/cpu: Update the comments of nr_cores and nr_dies, Zhao Liu, 2023/10/24
- [PATCH v5 05/20] i386/cpu: Fix i/d-cache topology to core level for Intel CPU, Zhao Liu, 2023/10/24
- [PATCH v5 06/20] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4], Zhao Liu, 2023/10/24
- [PATCH v5 07/20] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid(), Zhao Liu, 2023/10/24
- [PATCH v5 08/20] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB], Zhao Liu, 2023/10/24
- [PATCH v5 09/20] i386: Decouple CPUID[0x1F] subleaf with specific topology level,
Zhao Liu <=
- [PATCH v5 10/20] i386: Introduce module-level cpu topology to CPUX86State, Zhao Liu, 2023/10/24
- [PATCH v5 12/20] i386: Expose module level in CPUID[0x1F], Zhao Liu, 2023/10/24
- [PATCH v5 11/20] i386: Support modules_per_die in X86CPUTopoInfo, Zhao Liu, 2023/10/24
- [PATCH v5 14/20] i386/cpu: Introduce cluster-id to X86CPU, Zhao Liu, 2023/10/24
- [PATCH v5 13/20] i386: Support module_id in X86CPUTopoIDs, Zhao Liu, 2023/10/24
- [PATCH v5 15/20] tests: Add test case of APIC ID for module level parsing, Zhao Liu, 2023/10/24
- [PATCH v5 16/20] hw/i386/pc: Support smp.clusters for x86 PC machine, Zhao Liu, 2023/10/24
- [PATCH v5 17/20] i386: Add cache topology info in CPUCacheInfo, Zhao Liu, 2023/10/24
- [PATCH v5 19/20] i386: Use offsets get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14], Zhao Liu, 2023/10/24
- [PATCH v5 18/20] i386: Use CPUCacheInfo.share_level to encode CPUID[4], Zhao Liu, 2023/10/24