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[PULL v3 03/38] tcg/ppc: Reinterpret tb-relative to TB+4
From: |
Richard Henderson |
Subject: |
[PULL v3 03/38] tcg/ppc: Reinterpret tb-relative to TB+4 |
Date: |
Mon, 23 Oct 2023 11:12:54 -0700 |
It saves one insn to load the address of TB+4 instead of TB.
Adjust all of the indexing to match.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 9197cfd6c6..aafbf2db4e 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -215,6 +215,12 @@ static const int tcg_target_callee_save_regs[] = {
TCG_REG_R31
};
+/* For PPC, we use TB+4 instead of TB as the base. */
+static inline ptrdiff_t ppc_tbrel_diff(TCGContext *s, const void *target)
+{
+ return tcg_tbrel_diff(s, target) - 4;
+}
+
static inline bool in_range_b(tcg_target_long target)
{
return target == sextract64(target, 0, 26);
@@ -991,7 +997,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type,
TCGReg ret,
}
/* Load addresses within the TB with one insn. */
- tb_diff = tcg_tbrel_diff(s, (void *)arg);
+ tb_diff = ppc_tbrel_diff(s, (void *)arg);
if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) {
tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff));
return;
@@ -1044,7 +1050,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type,
TCGReg ret,
/* Use the constant pool, if possible. */
if (!in_prologue && USE_REG_TB) {
new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr,
- tcg_tbrel_diff(s, NULL));
+ ppc_tbrel_diff(s, NULL));
tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0));
return;
}
@@ -1104,7 +1110,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
unsigned vece,
*/
if (USE_REG_TB) {
rel = R_PPC_ADDR16;
- add = tcg_tbrel_diff(s, NULL);
+ add = ppc_tbrel_diff(s, NULL);
} else {
rel = R_PPC_ADDR32;
add = 0;
@@ -2531,7 +2537,6 @@ static void tcg_out_tb_start(TCGContext *s)
/* bcl 20,31,$+4 (preferred form for getting nia) */
tcg_out32(s, BC | BO_ALWAYS | BI(7, CR_SO) | 0x4 | LK);
tcg_out32(s, MFSPR | RT(TCG_REG_TB) | LR);
- tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, -4));
}
}
@@ -2551,7 +2556,7 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
/* When branch is out of range, fall through to indirect. */
if (USE_REG_TB) {
- ptrdiff_t offset = tcg_tbrel_diff(s, (void *)ptr);
+ ptrdiff_t offset = ppc_tbrel_diff(s, (void *)ptr);
tcg_out_mem_long(s, LD, LDX, TCG_REG_TMP1, TCG_REG_TB, offset);
} else {
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, ptr - (int16_t)ptr);
--
2.34.1
- [PULL v3 00/38] tcg patch queue, Richard Henderson, 2023/10/23
- [PULL v3 01/38] tcg/ppc: Untabify tcg-target.c.inc, Richard Henderson, 2023/10/23
- [PULL v3 02/38] tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TB, Richard Henderson, 2023/10/23
- [PULL v3 03/38] tcg/ppc: Reinterpret tb-relative to TB+4,
Richard Henderson <=
- [PULL v3 06/38] tcg/ppc: Use ADDPCIS for the constant pool, Richard Henderson, 2023/10/23
- [PULL v3 09/38] tcg/ppc: Use prefixed instructions in tcg_out_mem_long, Richard Henderson, 2023/10/23
- [PULL v3 04/38] tcg/ppc: Use ADDPCIS in tcg_out_tb_start, Richard Henderson, 2023/10/23
- [PULL v3 08/38] tcg/ppc: Use PADDI in tcg_out_movi, Richard Henderson, 2023/10/23
- [PULL v3 12/38] tcg/ppc: Use PLD in tcg_out_goto_tb, Richard Henderson, 2023/10/23
- [PULL v3 11/38] tcg/ppc: Use prefixed instructions in tcg_out_dupi_vec, Richard Henderson, 2023/10/23
- [PULL v3 10/38] tcg/ppc: Use PLD in tcg_out_movi for constant pool, Richard Henderson, 2023/10/23
- [PULL v3 05/38] tcg/ppc: Use ADDPCIS in tcg_out_movi_int, Richard Henderson, 2023/10/23
- [PULL v3 07/38] tcg/ppc: Use ADDPCIS in tcg_out_goto_tb, Richard Henderson, 2023/10/23
- [PULL v3 14/38] tcg: Introduce tcg_use_softmmu, Richard Henderson, 2023/10/23