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[PULL 62/83] hw/isa/piix: Allow for optional PIC creation in PIIX3
From: |
Michael S. Tsirkin |
Subject: |
[PULL 62/83] hw/isa/piix: Allow for optional PIC creation in PIIX3 |
Date: |
Wed, 18 Oct 2023 11:58:03 -0400 |
From: Bernhard Beschow <shentey@gmail.com>
In the PC machine, the PIC is created in board code to allow it to be
virtualized with various virtualization techniques. So explicitly disable its
creation in the PC machine via a property which defaults to enabled. Once the
PIIX implementations are consolidated this default will keep Malta working
without further ado.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-21-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/southbridge/piix.h | 1 +
hw/i386/pc_piix.c | 2 ++
hw/isa/piix.c | 21 +++++++++++++++++++--
3 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index dd5f7b31c0..08491693b4 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -69,6 +69,7 @@ struct PIIXState {
MemoryRegion rcr_mem;
bool has_acpi;
+ bool has_pic;
bool has_usb;
bool smm_enabled;
};
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 70cffcfe4f..fa39afd891 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -268,6 +268,8 @@ static void pc_init1(MachineState *machine,
object_property_set_bool(OBJECT(pci_dev), "has-acpi",
x86_machine_is_acpi_enabled(x86ms),
&error_abort);
+ object_property_set_bool(OBJECT(pci_dev), "has-pic", false,
+ &error_abort);
qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100);
object_property_set_bool(OBJECT(pci_dev), "smm-enabled",
x86_machine_is_smm_enabled(x86ms),
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index f6da334c6f..d6d9ac6473 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -106,7 +106,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int
level)
}
}
-static void piix4_request_i8259_irq(void *opaque, int irq, int level)
+static void piix_request_i8259_irq(void *opaque, int irq, int level)
{
PIIX4State *s = opaque;
qemu_set_irq(s->cpu_intr, level);
@@ -343,6 +343,22 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
memory_region_add_subregion_overlap(pci_address_space_io(dev),
PIIX_RCR_IOPORT, &d->rcr_mem, 1);
+ /* PIC */
+ if (d->has_pic) {
+ qemu_irq *i8259_out_irq = qemu_allocate_irqs(piix_request_i8259_irq, d,
+ 1);
+ qemu_irq *i8259 = i8259_init(isa_bus, *i8259_out_irq);
+ size_t i;
+
+ for (i = 0; i < ISA_NUM_IRQS; i++) {
+ d->isa_irqs_in[i] = i8259[i];
+ }
+
+ g_free(i8259);
+
+ qdev_init_gpio_out_named(DEVICE(dev), &d->cpu_intr, "intr", 1);
+ }
+
isa_bus_register_input_irqs(isa_bus, d->isa_irqs_in);
i8257_dma_init(isa_bus, 0);
@@ -419,6 +435,7 @@ static void pci_piix3_init(Object *obj)
static Property pci_piix3_props[] = {
DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0),
DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true),
+ DEFINE_PROP_BOOL("has-pic", PIIXState, has_pic, true),
DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true),
DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false),
DEFINE_PROP_END_OF_LIST(),
@@ -514,7 +531,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
PIIX_RCR_IOPORT, &s->rcr_mem, 1);
/* initialize i8259 pic */
- i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
+ i8259_out_irq = qemu_allocate_irqs(piix_request_i8259_irq, s, 1);
i8259 = i8259_init(isa_bus, *i8259_out_irq);
for (i = 0; i < ISA_NUM_IRQS; i++) {
--
MST
- [PULL 45/83] hw/i386/pc_piix: Assign PIIX3's ISA interrupts before its realize(), (continued)
- [PULL 45/83] hw/i386/pc_piix: Assign PIIX3's ISA interrupts before its realize(), Michael S. Tsirkin, 2023/10/18
- [PULL 47/83] hw/i386/pc_piix: Wire PIIX3's ISA interrupts by new "isa-irqs" property, Michael S. Tsirkin, 2023/10/18
- [PULL 49/83] hw/isa/piix3: Rename "pic" attribute to "isa_irqs_in", Michael S. Tsirkin, 2023/10/18
- [PULL 53/83] hw/isa/piix3: Create IDE controller in host device, Michael S. Tsirkin, 2023/10/18
- [PULL 58/83] hw/isa/piix4: Rename "isa" attribute to "isa_irqs_in", Michael S. Tsirkin, 2023/10/18
- [PULL 54/83] hw/isa/piix3: Create USB controller in host device, Michael S. Tsirkin, 2023/10/18
- [PULL 57/83] hw/isa/piix4: Remove unused inbound ISA interrupt lines, Michael S. Tsirkin, 2023/10/18
- [PULL 59/83] hw/isa/piix4: Rename reset control operations to match PIIX3, Michael S. Tsirkin, 2023/10/18
- [PULL 61/83] hw/isa/piix3: Merge hw/isa/piix4.c, Michael S. Tsirkin, 2023/10/18
- [PULL 56/83] hw/isa/piix3: Drop the "3" from PIIX base class name, Michael S. Tsirkin, 2023/10/18
- [PULL 62/83] hw/isa/piix: Allow for optional PIC creation in PIIX3,
Michael S. Tsirkin <=
- [PULL 55/83] hw/isa/piix3: Create power management controller in host device, Michael S. Tsirkin, 2023/10/18
- [PULL 64/83] hw/isa/piix: Harmonize names of reset control memory regions, Michael S. Tsirkin, 2023/10/18
- [PULL 66/83] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4, Michael S. Tsirkin, 2023/10/18
- [PULL 67/83] hw/isa/piix: Rename functions to be shared for PCI interrupt triggering, Michael S. Tsirkin, 2023/10/18
- [PULL 65/83] hw/isa/piix: Share PIIX3's base class with PIIX4, Michael S. Tsirkin, 2023/10/18
- [PULL 69/83] hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring, Michael S. Tsirkin, 2023/10/18
- [PULL 63/83] hw/isa/piix: Allow for optional PIT creation in PIIX3, Michael S. Tsirkin, 2023/10/18
- [PULL 71/83] hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine, Michael S. Tsirkin, 2023/10/18
- [PULL 60/83] hw/isa/piix4: Reuse struct PIIXState from PIIX3, Michael S. Tsirkin, 2023/10/18
- [PULL 68/83] hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4, Michael S. Tsirkin, 2023/10/18