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[PULL 31/54] target/riscv: make riscv_add_satp_mode_properties() public
From: |
Alistair Francis |
Subject: |
[PULL 31/54] target/riscv: make riscv_add_satp_mode_properties() public |
Date: |
Thu, 12 Oct 2023 14:10:28 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
This function is used for both accelerators. Make it public, and call it
from kvm_riscv_cpu_add_kvm_properties(). This will make it easier to
split KVM specific code for the KVM accelerator class in the next patch.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 5 ++---
target/riscv/kvm.c | 1 +
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0afa45aad1..d4b4ac3481 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -726,6 +726,7 @@ extern const RISCVCPUMultiExtConfig
riscv_cpu_experimental_exts[];
extern Property riscv_cpu_options[];
void riscv_cpu_add_misa_properties(Object *cpu_obj);
+void riscv_add_satp_mode_properties(Object *obj);
/* CSR function table */
extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c73500151f..143fbc1fbc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1115,7 +1115,7 @@ static void cpu_riscv_set_satp(Object *obj, Visitor *v,
const char *name,
satp_map->init |= 1 << satp;
}
-static void riscv_add_satp_mode_properties(Object *obj)
+void riscv_add_satp_mode_properties(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
@@ -1585,12 +1585,11 @@ static void riscv_cpu_add_multiext_prop_array(Object
*obj,
static void riscv_cpu_add_user_properties(Object *obj)
{
#ifndef CONFIG_USER_ONLY
- riscv_add_satp_mode_properties(obj);
-
if (kvm_enabled()) {
kvm_riscv_cpu_add_kvm_properties(obj);
return;
}
+ riscv_add_satp_mode_properties(obj);
#endif
riscv_cpu_add_misa_properties(obj);
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index e682a70311..e5e957121f 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -1323,6 +1323,7 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
DeviceState *dev = DEVICE(obj);
riscv_init_user_properties(obj);
+ riscv_add_satp_mode_properties(obj);
riscv_cpu_add_misa_properties(obj);
riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
--
2.41.0
- [PULL 21/54] target/riscv: Clear CSR values at reset and sync MPSTATE with host, (continued)
- [PULL 21/54] target/riscv: Clear CSR values at reset and sync MPSTATE with host, Alistair Francis, 2023/10/12
- [PULL 22/54] disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14, Alistair Francis, 2023/10/12
- [PULL 23/54] target/riscv: introduce TCG AccelCPUClass, Alistair Francis, 2023/10/12
- [PULL 24/54] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn(), Alistair Francis, 2023/10/12
- [PULL 26/54] target/riscv: move riscv_tcg_ops to tcg-cpu.c, Alistair Francis, 2023/10/12
- [PULL 25/54] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c, Alistair Francis, 2023/10/12
- [PULL 27/54] target/riscv/cpu.c: add .instance_post_init(), Alistair Francis, 2023/10/12
- [PULL 28/54] target/riscv: move 'host' CPU declaration to kvm.c, Alistair Francis, 2023/10/12
- [PULL 29/54] target/riscv/cpu.c: mark extensions arrays as 'const', Alistair Francis, 2023/10/12
- [PULL 30/54] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c, Alistair Francis, 2023/10/12
- [PULL 31/54] target/riscv: make riscv_add_satp_mode_properties() public,
Alistair Francis <=
- [PULL 32/54] target/riscv: remove kvm-stub.c, Alistair Francis, 2023/10/12
- [PULL 33/54] target/riscv: introduce KVM AccelCPUClass, Alistair Francis, 2023/10/12
- [PULL 34/54] target/riscv: move KVM only files to kvm subdir, Alistair Francis, 2023/10/12
- [PULL 35/54] target/riscv/kvm: do not use riscv_cpu_add_misa_properties(), Alistair Francis, 2023/10/12
- [PULL 36/54] target/riscv/cpu.c: export set_misa(), Alistair Francis, 2023/10/12
- [PULL 37/54] target/riscv/tcg: introduce tcg_cpu_instance_init(), Alistair Francis, 2023/10/12
- [PULL 38/54] target/riscv/cpu.c: make misa_ext_cfgs[] 'const', Alistair Francis, 2023/10/12
- [PULL 39/54] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c, Alistair Francis, 2023/10/12
- [PULL 40/54] target/riscv/cpu.c: export isa_edata_arr[], Alistair Francis, 2023/10/12
- [PULL 41/54] target/riscv/cpu: move priv spec functions to tcg-cpu.c, Alistair Francis, 2023/10/12