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[PULL 00/54] riscv-to-apply queue
From: |
Alistair Francis |
Subject: |
[PULL 00/54] riscv-to-apply queue |
Date: |
Thu, 12 Oct 2023 14:09:57 +1000 |
The following changes since commit a51e5124a655b3dad80b36b18547cb1eca2c5eb2:
Merge tag 'pull-omnibus-111023-1' of https://gitlab.com/stsquad/qemu into
staging (2023-10-11 09:43:10 -0400)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20231012-1
for you to fetch changes up to 837570cef237b634eb4c245363470deebea7089d:
target/riscv: Fix vfwmaccbf16.vf (2023-10-12 12:50:13 +1000)
----------------------------------------------------------------
Second RISC-V PR for 8.2
* Add support for the max CPU
* Detect user choice in TCG
* Clear CSR values at reset and sync MPSTATE with host
* Fix the typo of inverted order of pmpaddr13 and pmpaddr14
* Split TCG/KVM accelerators from cpu.c
* Add extension properties for all cpus
* Replace GDB exit calls with proper shutdown
* Support KVM_GET_REG_LIST
* Remove RVG warning
* Use env_archcpu for better performance
* Deprecate capital 'Z' CPU properties
* Fix vfwmaccbf16.vf
----------------------------------------------------------------
Alvin Chang (1):
disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14
Clément Chigot (5):
softmmu: add means to pass an exit code when requesting a shutdown
softmmu: pass the main loop status to gdb "Wxx" packet
hw/misc/sifive_test.c: replace exit calls with proper shutdown
hw/char: riscv_htif: replace exit calls with proper shutdown
gdbstub: replace exit calls with proper shutdown for softmmu
Daniel Henrique Barboza (45):
target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
target/riscv/cpu.c: skip 'bool' check when filtering KVM props
target/riscv/cpu.c: split kvm prop handling to its own helper
target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]
target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]
target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()
target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()
target/riscv/cpu.c: limit cfg->vext_spec log message
target/riscv: add 'max' CPU type
avocado, risc-v: add tuxboot tests for 'max' CPU
target/riscv: deprecate the 'any' CPU type
target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled
target/riscv: make CPUCFG() macro public
target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()
target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()
target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig
target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()
target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()
target/riscv/cpu.c: consider user option with RVG
target/riscv: introduce TCG AccelCPUClass
target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()
target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c
target/riscv: move riscv_tcg_ops to tcg-cpu.c
target/riscv/cpu.c: add .instance_post_init()
target/riscv: move 'host' CPU declaration to kvm.c
target/riscv/cpu.c: mark extensions arrays as 'const'
target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c
target/riscv: make riscv_add_satp_mode_properties() public
target/riscv: remove kvm-stub.c
target/riscv: introduce KVM AccelCPUClass
target/riscv: move KVM only files to kvm subdir
target/riscv/kvm: do not use riscv_cpu_add_misa_properties()
target/riscv/cpu.c: export set_misa()
target/riscv/tcg: introduce tcg_cpu_instance_init()
target/riscv/cpu.c: make misa_ext_cfgs[] 'const'
target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c
target/riscv/cpu.c: export isa_edata_arr[]
target/riscv/cpu: move priv spec functions to tcg-cpu.c
target/riscv: add riscv_cpu_get_name()
target/riscv/tcg-cpu.c: add extension properties for all cpus
target/riscv/kvm: improve 'init_multiext_cfg' error msg
target/riscv/kvm: support KVM_GET_REG_LIST
target/riscv/tcg: remove RVG warning
target/riscv: deprecate capital 'Z' CPU properties
Max Chou (1):
target/riscv: Fix vfwmaccbf16.vf
Richard W.M. Jones (1):
target/riscv: Use env_archcpu for better performance
liguang.zhang (1):
target/riscv: Clear CSR values at reset and sync MPSTATE with host
docs/about/deprecated.rst | 35 ++
include/gdbstub/syscalls.h | 9 +
include/sysemu/runstate.h | 2 +
include/sysemu/sysemu.h | 2 +-
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.h | 34 +-
target/riscv/{ => kvm}/kvm_riscv.h | 2 +-
target/riscv/tcg/tcg-cpu.h | 27 +
disas/riscv.c | 4 +-
gdbstub/gdbstub.c | 5 +-
gdbstub/system.c | 6 +
gdbstub/user.c | 6 +
hw/char/riscv_htif.c | 5 +-
hw/intc/riscv_aplic.c | 2 +-
hw/misc/sifive_test.c | 9 +-
hw/riscv/virt.c | 2 +-
system/main.c | 2 +-
system/runstate.c | 16 +-
target/riscv/cpu.c | 1030 +++++++--------------------------
target/riscv/cpu_helper.c | 3 +-
target/riscv/csr.c | 1 +
target/riscv/kvm-stub.c | 30 -
target/riscv/{kvm.c => kvm/kvm-cpu.c} | 272 ++++++++-
target/riscv/tcg/tcg-cpu.c | 949 ++++++++++++++++++++++++++++++
target/riscv/vector_helper.c | 2 +-
target/riscv/kvm/meson.build | 1 +
target/riscv/meson.build | 4 +-
target/riscv/tcg/meson.build | 2 +
tests/avocado/tuxrun_baselines.py | 32 +
29 files changed, 1604 insertions(+), 891 deletions(-)
rename target/riscv/{ => kvm}/kvm_riscv.h (95%)
create mode 100644 target/riscv/tcg/tcg-cpu.h
delete mode 100644 target/riscv/kvm-stub.c
rename target/riscv/{kvm.c => kvm/kvm-cpu.c} (81%)
create mode 100644 target/riscv/tcg/tcg-cpu.c
create mode 100644 target/riscv/kvm/meson.build
create mode 100644 target/riscv/tcg/meson.build
- [PULL 00/54] riscv-to-apply queue,
Alistair Francis <=
- [PULL 01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[], Alistair Francis, 2023/10/12
- [PULL 02/54] target/riscv/cpu.c: skip 'bool' check when filtering KVM props, Alistair Francis, 2023/10/12
- [PULL 03/54] target/riscv/cpu.c: split kvm prop handling to its own helper, Alistair Francis, 2023/10/12
- [PULL 04/54] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[], Alistair Francis, 2023/10/12
- [PULL 05/54] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[], Alistair Francis, 2023/10/12
- [PULL 08/54] target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array(), Alistair Francis, 2023/10/12
- [PULL 07/54] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array(), Alistair Francis, 2023/10/12
- [PULL 11/54] avocado, risc-v: add tuxboot tests for 'max' CPU, Alistair Francis, 2023/10/12
- [PULL 10/54] target/riscv: add 'max' CPU type, Alistair Francis, 2023/10/12
- [PULL 12/54] target/riscv: deprecate the 'any' CPU type, Alistair Francis, 2023/10/12