[PATCH v4] hw/isa/vt82c686: Respect SCI interrupt assignment

[BALATON Zoltan]

According to the datasheet, SCI interrupts of the power management
function aren't routed through the PCI pins but rather directly to the
integrated PIC. The routing is configurable through the ACPI interrupt
select register at offset 0x42 in the PCI configuration space of the
power management function.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
Alternative proposal to Bernhard's patch to remove FIXME about SCI.

Apply this on top of reverting commit 4e5a20b6da9 which could also be
squashed in this patch but I let you decide if you want that as
separete commit or part of this. I did not test this beyond compiling
but I think this is all there is to it. (Overusing QOM within a chip
model does not make sense as QOM is meant to allow users to introspect
and configure device models and combine different models into new
machines eventually without modifying QEMU but this is not applicable
here within a single device model that can be considered as friend
classes so don't go oveboard with it when not needed.)

 hw/isa/vt82c686.c | 30 +++++++++++++-----------------
 1 file changed, 13 insertions(+), 17 deletions(-)

diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 8016c71315..2eb769c7fa 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -140,25 +140,21 @@ static const MemoryRegionOps pm_io_ops = {
 
 static void pm_update_sci(ViaPMState *s)
 {
-    int sci_level, pmsts;
+    int sci_irq, pmsts;
 
     pmsts = acpi_pm1_evt_get_sts(&s->ar);
-    sci_level = (((pmsts & s->ar.pm1.evt.en) &
-                  (ACPI_BITMASK_RT_CLOCK_ENABLE |
-                   ACPI_BITMASK_POWER_BUTTON_ENABLE |
-                   ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
-                   ACPI_BITMASK_TIMER_ENABLE)) != 0);
-    if (pci_get_byte(s->dev.config + PCI_INTERRUPT_PIN)) {
-        /*
-         * FIXME:
-         * Fix device model that realizes this PM device and remove
-         * this work around.
-         * The device model should wire SCI and setup
-         * PCI_INTERRUPT_PIN properly.
-         * If PIN# = 0(interrupt pin isn't used), don't raise SCI as
-         * work around.
-         */
-        pci_set_irq(&s->dev, sci_level);
+    sci_irq = pci_get_byte(s->dev.config + 0x42) & 0xf;
+    if (sci_irq) {
+        int sci_level = (((pmsts & s->ar.pm1.evt.en) &
+                          (ACPI_BITMASK_RT_CLOCK_ENABLE |
+                              ACPI_BITMASK_POWER_BUTTON_ENABLE |
+                              ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
+                              ACPI_BITMASK_TIMER_ENABLE)) != 0);
+
+        if (sci_irq == 2) {
+            qemu_log_mask(LOG_GUEST_ERROR, "IRQ 2 for VIA PM SCI is reserved");
+        }
+        via_isa_set_irq(pci_get_function_0(&s->dev), sci_irq, sci_level);
     }
     /* schedule a timer interruption if needed */
     acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) 
&&
-- 
2.30.9