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[Stable-7.2.5 19/36] linux-user/armeb: Fix __kernel_cmpxchg() for armeb
From: |
Michael Tokarev |
Subject: |
[Stable-7.2.5 19/36] linux-user/armeb: Fix __kernel_cmpxchg() for armeb |
Date: |
Fri, 4 Aug 2023 21:53:32 +0300 |
From: Helge Deller <deller@gmx.de>
Commit 7f4f0d9ea870 ("linux-user/arm: Implement __kernel_cmpxchg with host
atomics") switched to use qatomic_cmpxchg() to swap a word with the memory
content, but missed to endianess-swap the oldval and newval values when
emulating an armeb CPU, which expects words to be stored in big endian in
the guest memory.
The bug can be verified with qemu >= v7.0 on any little-endian host, when
starting the armeb binary of the upx program, which just hangs without
this patch.
Cc: qemu-stable@nongnu.org
Signed-off-by: Helge Deller <deller@gmx.de>
Reported-by: "Markus F.X.J. Oberhumer" <markus@oberhumer.com>
Reported-by: John Reiser <jreiser@BitWagon.com>
Closes: https://github.com/upx/upx/issues/687
Message-Id: <ZMQVnqY+F+5sTNFd@p100>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
(cherry picked from commit 38dd78c41eaf08b490c9e7ec68fc508bbaa5cb1d)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
index c0790f3246..85804c367a 100644
--- a/linux-user/arm/cpu_loop.c
+++ b/linux-user/arm/cpu_loop.c
@@ -117,8 +117,9 @@ static void arm_kernel_cmpxchg32_helper(CPUARMState *env)
{
uint32_t oldval, newval, val, addr, cpsr, *host_addr;
- oldval = env->regs[0];
- newval = env->regs[1];
+ /* Swap if host != guest endianness, for the host cmpxchg below */
+ oldval = tswap32(env->regs[0]);
+ newval = tswap32(env->regs[1]);
addr = env->regs[2];
mmap_lock();
@@ -174,6 +175,10 @@ static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
return;
}
+ /* Swap if host != guest endianness, for the host cmpxchg below */
+ oldval = tswap64(oldval);
+ newval = tswap64(newval);
+
#ifdef CONFIG_ATOMIC64
val = qatomic_cmpxchg__nocheck(host_addr, oldval, newval);
cpsr = (val == oldval) * CPSR_C;
--
2.39.2
- [PULL 00/24] target-arm queue, Peter Maydell, 2023/08/31
- [PULL 01/24] target/arm: Reduce dcz_blocksize to uint8_t, Peter Maydell, 2023/08/31
- [PULL 04/24] target/arm: When tag memory is not present, set MTE=1, Peter Maydell, 2023/08/31
- [PULL 03/24] target/arm: Support more GM blocksizes, Peter Maydell, 2023/08/31
- [PULL 02/24] target/arm: Allow cpu to configure GM blocksize, Peter Maydell, 2023/08/31
- [PULL 07/24] target/arm: Apply access checks to neoverse-v1 special registers, Peter Maydell, 2023/08/31
- [PULL 06/24] target/arm: Apply access checks to neoverse-n1 special registers, Peter Maydell, 2023/08/31
- [PULL 09/24] target/arm: Implement FEAT_HPDS2 as a no-op, Peter Maydell, 2023/08/31
- [PULL 10/24] target/arm: properly document FEAT_CRC32, Peter Maydell, 2023/08/31
- [PULL 13/24] Add i.MX6UL missing devices., Peter Maydell, 2023/08/31
- [PULL 14/24] Refactor i.MX7 processor code, Peter Maydell, 2023/08/31