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[PULL 10/24] target/arm: properly document FEAT_CRC32
From: |
Peter Maydell |
Subject: |
[PULL 10/24] target/arm: properly document FEAT_CRC32 |
Date: |
Thu, 31 Aug 2023 11:45:05 +0100 |
From: Alex Bennée <alex.bennee@linaro.org>
This is a mandatory feature for Armv8.1 architectures but we don't
state the feature clearly in our emulation list. Also include
FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org
Cc: qemu-stable@nongnu.org
Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org>
[PMM: pluralize 'instructions' in docs]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 2012bbf7c7c..2e6a7c8961e 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -14,6 +14,7 @@ the following architecture extensions:
- FEAT_BBM at level 2 (Translation table break-before-make levels)
- FEAT_BF16 (AArch64 BFloat16 instructions)
- FEAT_BTI (Branch Target Identification)
+- FEAT_CRC32 (CRC32 instructions)
- FEAT_CSV2 (Cache speculation variant 2)
- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 11e406d960e..0f8972950d6 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -788,7 +788,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
- t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* FEAT_CRC32 */
t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */
t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */
t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */
--
2.34.1
- [PULL 00/24] target-arm queue, Peter Maydell, 2023/08/31
- [PULL 01/24] target/arm: Reduce dcz_blocksize to uint8_t, Peter Maydell, 2023/08/31
- [PULL 04/24] target/arm: When tag memory is not present, set MTE=1, Peter Maydell, 2023/08/31
- [PULL 03/24] target/arm: Support more GM blocksizes, Peter Maydell, 2023/08/31
- [PULL 02/24] target/arm: Allow cpu to configure GM blocksize, Peter Maydell, 2023/08/31
- [PULL 07/24] target/arm: Apply access checks to neoverse-v1 special registers, Peter Maydell, 2023/08/31
- [PULL 06/24] target/arm: Apply access checks to neoverse-n1 special registers, Peter Maydell, 2023/08/31
- [PULL 09/24] target/arm: Implement FEAT_HPDS2 as a no-op, Peter Maydell, 2023/08/31
- [PULL 10/24] target/arm: properly document FEAT_CRC32,
Peter Maydell <=
- [PULL 13/24] Add i.MX6UL missing devices., Peter Maydell, 2023/08/31
- [PULL 14/24] Refactor i.MX7 processor code, Peter Maydell, 2023/08/31
- [PULL 08/24] target/arm: Suppress FEAT_TRBE (Trace Buffer Extension), Peter Maydell, 2023/08/31
- [PULL 12/24] Refactor i.MX6UL processor code, Peter Maydell, 2023/08/31
- [PULL 21/24] rtc: Use time_t for passing and returning time offsets, Peter Maydell, 2023/08/31
- [PULL 15/24] Add i.MX7 missing TZ devices and memory regions, Peter Maydell, 2023/08/31
- [PULL 16/24] Add i.MX7 SRC device implementation, Peter Maydell, 2023/08/31
- [PULL 24/24] hw/arm: Set number of MPU regions correctly for an505, an521, an524, Peter Maydell, 2023/08/31
- [PULL 23/24] hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties, Peter Maydell, 2023/08/31
- [PULL 17/24] target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS, Peter Maydell, 2023/08/31