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[PULL 7/7] target/arm: Two fixes for secure ptw
From: |
Peter Maydell |
Subject: |
[PULL 7/7] target/arm: Two fixes for secure ptw |
Date: |
Fri, 4 Nov 2022 11:35:15 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
Reversed the sense of non-secure in get_phys_addr_lpae,
and failed to initialize attrs.secure for ARMMMUIdx_Phys_S.
Fixes: 48da29e4 ("target/arm: Add ptw_idx to S1Translate")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1293
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index e04dccff44f..3745ac97234 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1381,7 +1381,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
descaddr |= (address >> (stride * (4 - level))) & indexmask;
descaddr &= ~7ULL;
nstable = extract32(tableattrs, 4, 1);
- if (!nstable) {
+ if (nstable) {
/*
* Stage2_S -> Stage2 or Phys_S -> Phys_NS
* Assert that the non-secure idx are even, and relative order.
@@ -2695,6 +2695,13 @@ static bool get_phys_addr_with_struct(CPUARMState *env,
S1Translate *ptw,
bool is_secure = ptw->in_secure;
ARMMMUIdx s1_mmu_idx;
+ /*
+ * The page table entries may downgrade secure to non-secure, but
+ * cannot upgrade an non-secure translation regime's attributes
+ * to secure.
+ */
+ result->f.attrs.secure = is_secure;
+
switch (mmu_idx) {
case ARMMMUIdx_Phys_S:
case ARMMMUIdx_Phys_NS:
@@ -2736,12 +2743,6 @@ static bool get_phys_addr_with_struct(CPUARMState *env,
S1Translate *ptw,
break;
}
- /*
- * The page table entries may downgrade secure to non-secure, but
- * cannot upgrade an non-secure translation regime's attributes
- * to secure.
- */
- result->f.attrs.secure = is_secure;
result->f.attrs.user = regime_is_user(env, mmu_idx);
/*
--
2.25.1
- [PULL 0/7] target-arm queue, Peter Maydell, 2022/11/04
- [PULL 1/7] hw/arm/boot: Set SME and SVE EL3 vector lengths when booting kernel, Peter Maydell, 2022/11/04
- [PULL 2/7] hw/arm/boot: Set SCR_EL3.HXEn when booting kernel, Peter Maydell, 2022/11/04
- [PULL 3/7] target/arm: Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB, Peter Maydell, 2022/11/04
- [PULL 6/7] target/arm: Honor HCR_E2H and HCR_TGE in ats_write64(), Peter Maydell, 2022/11/04
- [PULL 4/7] target/arm: Fix Privileged Access Never (PAN) for aarch32, Peter Maydell, 2022/11/04
- [PULL 5/7] target/arm: Copy the entire vector in DO_ZIP, Peter Maydell, 2022/11/04
- [PULL 7/7] target/arm: Two fixes for secure ptw,
Peter Maydell <=
- Re: [PULL 0/7] target-arm queue, Stefan Hajnoczi, 2022/11/07