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[PULL 2/7] hw/arm/boot: Set SCR_EL3.HXEn when booting kernel
From: |
Peter Maydell |
Subject: |
[PULL 2/7] hw/arm/boot: Set SCR_EL3.HXEn when booting kernel |
Date: |
Fri, 4 Nov 2022 11:35:10 +0000 |
When we direct boot a kernel on a CPU which emulates EL3, we need to
set up the EL3 system registers as the Linux kernel documentation
specifies:
https://www.kernel.org/doc/Documentation/arm64/booting.rst
For CPUs with FEAT_HCX support this includes:
- SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
but we forgot to do this when implementing FEAT_HCX, which would mean
that a guest trying to access the HCRX_EL2 register would crash.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221027140207.413084-3-peter.maydell@linaro.org
---
hw/arm/boot.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 17d38260faf..15c2bf1867f 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -771,6 +771,9 @@ static void do_cpu_reset(void *opaque)
env->cp15.scr_el3 |= SCR_ENTP2;
env->vfp.smcr_el[3] = 0xf;
}
+ if (cpu_isar_feature(aa64_hcx, cpu)) {
+ env->cp15.scr_el3 |= SCR_HXEN;
+ }
/* AArch64 kernels never boot in secure mode */
assert(!info->secure_boot);
/* This hook is only supported for AArch32 currently:
--
2.25.1
- [PULL 0/7] target-arm queue, Peter Maydell, 2022/11/04
- [PULL 1/7] hw/arm/boot: Set SME and SVE EL3 vector lengths when booting kernel, Peter Maydell, 2022/11/04
- [PULL 2/7] hw/arm/boot: Set SCR_EL3.HXEn when booting kernel,
Peter Maydell <=
- [PULL 3/7] target/arm: Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB, Peter Maydell, 2022/11/04
- [PULL 6/7] target/arm: Honor HCR_E2H and HCR_TGE in ats_write64(), Peter Maydell, 2022/11/04
- [PULL 4/7] target/arm: Fix Privileged Access Never (PAN) for aarch32, Peter Maydell, 2022/11/04
- [PULL 5/7] target/arm: Copy the entire vector in DO_ZIP, Peter Maydell, 2022/11/04
- [PULL 7/7] target/arm: Two fixes for secure ptw, Peter Maydell, 2022/11/04
- Re: [PULL 0/7] target-arm queue, Stefan Hajnoczi, 2022/11/07