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[PULL 02/10] target/arm: Make writes to MDCR_EL3 use PMU start/finish ca
From: |
Peter Maydell |
Subject: |
[PULL 02/10] target/arm: Make writes to MDCR_EL3 use PMU start/finish calls |
Date: |
Fri, 30 Sep 2022 14:35:03 +0100 |
In commit 01765386a88868 we fixed a bug where we weren't correctly
bracketing changes to some registers with pmu_op_start() and
pmu_op_finish() calls for changes which affect whether the PMU
counters might be enabled. However, we missed the case of writes to
the AArch64 MDCR_EL3 register, because (unlike its AArch32
counterpart) they are currently done directly to the CPU state struct
without going through the sdcr_write() function.
Give MDCR_EL3 a writefn which handles the PMU start/finish calls.
The SDCR writefn then simplfies to "call the MDCR_EL3 writefn after
masking off the bits which don't exist in the AArch32 register".
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220923123412.1214041-3-peter.maydell@linaro.org
---
target/arm/helper.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index fadeed0b6bb..24c592ffef8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4756,8 +4756,8 @@ static void sctlr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
}
}
-static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t value)
+static void mdcr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
{
/*
* Some MDCR_EL3 bits affect whether PMU counters are running:
@@ -4769,12 +4769,19 @@ static void sdcr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
if (pmu_op) {
pmu_op_start(env);
}
- env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
+ env->cp15.mdcr_el3 = value;
if (pmu_op) {
pmu_op_finish(env);
}
}
+static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
+ mdcr_el3_write(env, ri, value & SDCR_VALID_MASK);
+}
+
static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -5122,9 +5129,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.access = PL2_RW,
.fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
{ .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
+ .type = ARM_CP_IO,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
.resetvalue = 0,
- .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
+ .access = PL3_RW,
+ .writefn = mdcr_el3_write,
+ .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
{ .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
.cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
.access = PL1_RW, .accessfn = access_trap_aa32s_el1,
--
2.25.1
- [PULL 00/10] target-arm queue, Peter Maydell, 2022/09/30
- [PULL 01/10] target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO, Peter Maydell, 2022/09/30
- [PULL 04/10] target/arm: Rearrange cpu64.c so all the CPU initfns are together, Peter Maydell, 2022/09/30
- [PULL 05/10] hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers, Peter Maydell, 2022/09/30
- [PULL 06/10] hw/arm/virt: Fix devicetree warning about the root node, Peter Maydell, 2022/09/30
- [PULL 08/10] hw/arm/virt: Use "msi-map" devicetree property for PCI, Peter Maydell, 2022/09/30
- [PULL 07/10] hw/arm/virt: Fix devicetree warning about the GIC node, Peter Maydell, 2022/09/30
- [PULL 09/10] hw/arm/virt: Fix devicetree warning about the SMMU node, Peter Maydell, 2022/09/30
- [PULL 10/10] target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP, Peter Maydell, 2022/09/30
- [PULL 02/10] target/arm: Make writes to MDCR_EL3 use PMU start/finish calls,
Peter Maydell <=
- [PULL 03/10] target/arm: Update SDCR_VALID_MASK to include SCCD, Peter Maydell, 2022/09/30