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Re: [PATCH 27/37] target/i386: Use tcg gvec ops for pmovmskb
From: |
Paolo Bonzini |
Subject: |
Re: [PATCH 27/37] target/i386: Use tcg gvec ops for pmovmskb |
Date: |
Thu, 15 Sep 2022 00:59:50 +0200 |
On Tue, Sep 13, 2022 at 10:17 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 9/12/22 00:04, Paolo Bonzini wrote:
> > + while (vec_len > 8) {
> > + vec_len -= 8;
> > + tcg_gen_shli_tl(s->T0, s->T0, 8);
> > + tcg_gen_ld8u_tl(t, cpu_env, offsetof(CPUX86State,
> > xmm_t0.ZMM_B(vec_len - 1)));
> > + tcg_gen_or_tl(s->T0, s->T0, t);
> > }
>
> The shl + or is deposit, for those hosts that have it,
> and will be re-expanded to shl + or for those that don't:
>
> tcg_gen_ld8u_tl(t, ...);
> tcg_gen_deposit_tl(s->T0, t, s->T0, 8, TARGET_LONG_BITS - 8);
What you get from that is an shl(t, 56) followed by extract2 (i.e.
SHRD). Yeah there are targets with a native deposit (x86 itself could
add PDEP/PEXT support I guess) but I find it hard to believe that it
outperforms a simple shl + or.
If we want to get clever, I should instead load ZMM_B(vec_len - 1)
directly into the *high* byte of t, using ZMM_L or ZMM_Q, and then
issue the extract2 myself.
Paolo
- Re: [PATCH 20/37] target/i386: reimplement 0x0f 0x60-0x6f, add AVX, (continued)
- [PATCH 23/37] target/i386: reimplement 0x0f 0x78-0x7f, add AVX, Paolo Bonzini, 2022/09/11
- [PATCH 25/37] target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX, Paolo Bonzini, 2022/09/11
- [PATCH 24/37] target/i386: reimplement 0x0f 0x70-0x77, add AVX, Paolo Bonzini, 2022/09/11
- [PATCH 27/37] target/i386: Use tcg gvec ops for pmovmskb, Paolo Bonzini, 2022/09/11
- [PATCH 26/37] target/i386: reimplement 0x0f 0x3a, add AVX, Paolo Bonzini, 2022/09/11
- [PATCH 28/37] target/i386: reimplement 0x0f 0x38, add AVX, Paolo Bonzini, 2022/09/11
[PATCH 29/37] target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, add AVX, Paolo Bonzini, 2022/09/11
[PATCH 31/37] target/i386: reimplement 0x0f 0x28-0x2f, add AVX, Paolo Bonzini, 2022/09/11