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[PULL 27/44] target/riscv: Fix priority of csr related check in riscv_cs
From: |
Alistair Francis |
Subject: |
[PULL 27/44] target/riscv: Fix priority of csr related check in riscv_csrrw_check |
Date: |
Wed, 7 Sep 2022 10:03:36 +0200 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
Normally, riscv_csrrw_check is called when executing Zicsr instructions.
And we can only do access control for existed CSRs. So the priority of
CSR related check, from highest to lowest, should be as follows:
1) check whether Zicsr is supported: raise RISCV_EXCP_ILLEGAL_INST if not
2) check whether csr is existed: raise RISCV_EXCP_ILLEGAL_INST if not
3) do access control: raise RISCV_EXCP_ILLEGAL_INST or RISCV_EXCP_VIRT_
INSTRUCTION_FAULT if not allowed
The predicates contain parts of function of both 2) and 3), So they need
to be placed in the middle of riscv_csrrw_check
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220803123652.3700-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 44 +++++++++++++++++++++++++-------------------
1 file changed, 25 insertions(+), 19 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0fb042b2fd..d81f466c80 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3270,6 +3270,30 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
int read_only = get_field(csrno, 0xC00) == 3;
int csr_min_priv = csr_ops[csrno].min_priv_ver;
+
+ /* ensure the CSR extension is enabled. */
+ if (!cpu->cfg.ext_icsr) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ if (env->priv_ver < csr_min_priv) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ /* check predicate */
+ if (!csr_ops[csrno].predicate) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ if (write_mask && read_only) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ RISCVException ret = csr_ops[csrno].predicate(env, csrno);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+
#if !defined(CONFIG_USER_ONLY)
int csr_priv, effective_priv = env->priv;
@@ -3290,25 +3314,7 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
return RISCV_EXCP_ILLEGAL_INST;
}
#endif
- if (write_mask && read_only) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-
- /* ensure the CSR extension is enabled. */
- if (!cpu->cfg.ext_icsr) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-
- /* check predicate */
- if (!csr_ops[csrno].predicate) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-
- if (env->priv_ver < csr_min_priv) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-
- return csr_ops[csrno].predicate(env, csrno);
+ return RISCV_EXCP_NONE;
}
static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
--
2.37.2
- [PULL 25/44] target/riscv: Add Zihintpause support, (continued)
- [PULL 25/44] target/riscv: Add Zihintpause support, Alistair Francis, 2022/09/07
- [PULL 24/44] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior, Alistair Francis, 2022/09/07
- [PULL 26/44] hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec(), Alistair Francis, 2022/09/07
- [PULL 29/44] hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals, Alistair Francis, 2022/09/07
- [PULL 28/44] hw/riscv: opentitan: bump opentitan version, Alistair Francis, 2022/09/07
- [PULL 31/44] hw/riscv: virt: fix uart node name, Alistair Francis, 2022/09/07
- [PULL 35/44] target/riscv: Add xicondops in ISA entry, Alistair Francis, 2022/09/07
- [PULL 43/44] hw/riscv: virt: Add PMU DT node to the device tree, Alistair Francis, 2022/09/07
- [PULL 36/44] target/riscv: Use official extension names for AIA CSRs, Alistair Francis, 2022/09/07
- [PULL 34/44] hw/core: fix platform bus node name, Alistair Francis, 2022/09/07
- [PULL 27/44] target/riscv: Fix priority of csr related check in riscv_csrrw_check,
Alistair Francis <=
- [PULL 30/44] target/riscv: Remove additional priv version check for mcountinhibit, Alistair Francis, 2022/09/07
- [PULL 32/44] hw/riscv: virt: fix the plic's address cells, Alistair Francis, 2022/09/07
- [PULL 41/44] target/riscv: Simplify counter predicate function, Alistair Francis, 2022/09/07
- [PULL 42/44] target/riscv: Add few cache related PMU events, Alistair Francis, 2022/09/07
- [PULL 37/44] hw/intc: Move mtimer/mtimecmp to aclint, Alistair Francis, 2022/09/07
- [PULL 33/44] hw/riscv: virt: fix syscon subnode paths, Alistair Francis, 2022/09/07
- [PULL 38/44] target/riscv: Add stimecmp support, Alistair Francis, 2022/09/07
- [PULL 39/44] target/riscv: Add vstimecmp support, Alistair Francis, 2022/09/07
- [PULL 40/44] target/riscv: Add sscofpmf extension support, Alistair Francis, 2022/09/07
- [PULL 44/44] target/riscv: Update the privilege field for sscofpmf CSRs, Alistair Francis, 2022/09/07