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[PULL 29/44] hw/riscv: microchip_pfsoc: fix kernel panics due to missing
From: |
Alistair Francis |
Subject: |
[PULL 29/44] hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals |
Date: |
Wed, 7 Sep 2022 10:03:38 +0200 |
From: Conor Dooley <conor.dooley@microchip.com>
Booting using "Direct Kernel Boot" for PolarFire SoC & skipping u-boot
entirely is probably not advisable, but it does at least show signs of
life. Recent Linux kernel versions make use of peripherals that are
missing definitions in QEMU and lead to kernel panics. These issues
almost certain rear their head for other methods of booting, but I was
unable to figure out a suitable HSS version that is recent enough to
support these peripherals & works with QEMU.
With these peripherals added, booting a kernel with the following hangs
hangs waiting for the system controller's hwrng, but the kernel no
longer panics. With the Linux driver for hwrng disabled, it boots to
console.
qemu-system-riscv64 -M microchip-icicle-kit \
-m 2G -smp 5 \
-kernel $(vmlinux_bin) \
-dtb $(dtb)\
-initrd $(initramfs) \
-display none -serial null \
-serial stdio
More peripherals are added than strictly required to fix the panics in
the hopes of avoiding a replication of this problem in the future.
Some of the peripherals which are in the device tree for recent kernels
are implemented in the FPGA fabric. The eMMC/SD mux, which exists as
an unimplemented device is replaced by a wider entry. This updated
entry covers both the mux & the remainder of the FPGA fabric connected
to the MSS using Fabric Interrconnect (FIC) 3.
Link:
https://github.com/polarfire-soc/icicle-kit-reference-design#fabric-memory-map
Link:
https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/SupportingCollateral/V1_4_Register_Map.zip
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220813135127.2971754-1-mail@conchuod.ie>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/microchip_pfsoc.h | 14 ++++++-
hw/riscv/microchip_pfsoc.c | 67 +++++++++++++++++++++++++++---
2 files changed, 74 insertions(+), 7 deletions(-)
diff --git a/include/hw/riscv/microchip_pfsoc.h
b/include/hw/riscv/microchip_pfsoc.h
index a0673f5f59..a757b240e0 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -88,8 +88,11 @@ enum {
MICROCHIP_PFSOC_L2LIM,
MICROCHIP_PFSOC_PLIC,
MICROCHIP_PFSOC_MMUART0,
+ MICROCHIP_PFSOC_WDOG0,
MICROCHIP_PFSOC_SYSREG,
+ MICROCHIP_PFSOC_AXISW,
MICROCHIP_PFSOC_MPUCFG,
+ MICROCHIP_PFSOC_FMETER,
MICROCHIP_PFSOC_DDR_SGMII_PHY,
MICROCHIP_PFSOC_EMMC_SD,
MICROCHIP_PFSOC_DDR_CFG,
@@ -97,19 +100,28 @@ enum {
MICROCHIP_PFSOC_MMUART2,
MICROCHIP_PFSOC_MMUART3,
MICROCHIP_PFSOC_MMUART4,
+ MICROCHIP_PFSOC_WDOG1,
+ MICROCHIP_PFSOC_WDOG2,
+ MICROCHIP_PFSOC_WDOG3,
+ MICROCHIP_PFSOC_WDOG4,
MICROCHIP_PFSOC_SPI0,
MICROCHIP_PFSOC_SPI1,
+ MICROCHIP_PFSOC_I2C0,
MICROCHIP_PFSOC_I2C1,
+ MICROCHIP_PFSOC_CAN0,
+ MICROCHIP_PFSOC_CAN1,
MICROCHIP_PFSOC_GEM0,
MICROCHIP_PFSOC_GEM1,
MICROCHIP_PFSOC_GPIO0,
MICROCHIP_PFSOC_GPIO1,
MICROCHIP_PFSOC_GPIO2,
+ MICROCHIP_PFSOC_RTC,
MICROCHIP_PFSOC_ENVM_CFG,
MICROCHIP_PFSOC_ENVM_DATA,
+ MICROCHIP_PFSOC_USB,
MICROCHIP_PFSOC_QSPI_XIP,
MICROCHIP_PFSOC_IOSCB,
- MICROCHIP_PFSOC_EMMC_SD_MUX,
+ MICROCHIP_PFSOC_FABRIC_FIC3,
MICROCHIP_PFSOC_DRAM_LO,
MICROCHIP_PFSOC_DRAM_LO_ALIAS,
MICROCHIP_PFSOC_DRAM_HI,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 7313153606..a821263d4f 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -100,8 +100,11 @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
[MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
[MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
[MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
+ [MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 },
[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
+ [MICROCHIP_PFSOC_AXISW] = { 0x20004000, 0x1000 },
[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
+ [MICROCHIP_PFSOC_FMETER] = { 0x20006000, 0x1000 },
[MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 },
[MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
[MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 },
@@ -109,19 +112,28 @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
+ [MICROCHIP_PFSOC_WDOG1] = { 0x20101000, 0x1000 },
+ [MICROCHIP_PFSOC_WDOG2] = { 0x20103000, 0x1000 },
+ [MICROCHIP_PFSOC_WDOG3] = { 0x20105000, 0x1000 },
+ [MICROCHIP_PFSOC_WDOG4] = { 0x20106000, 0x1000 },
[MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 },
[MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 },
+ [MICROCHIP_PFSOC_I2C0] = { 0x2010a000, 0x1000 },
[MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 },
+ [MICROCHIP_PFSOC_CAN0] = { 0x2010c000, 0x1000 },
+ [MICROCHIP_PFSOC_CAN1] = { 0x2010d000, 0x1000 },
[MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
[MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
[MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 },
[MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 },
[MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
+ [MICROCHIP_PFSOC_RTC] = { 0x20124000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
+ [MICROCHIP_PFSOC_USB] = { 0x20201000, 0x1000 },
[MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
[MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
- [MICROCHIP_PFSOC_EMMC_SD_MUX] = { 0x4f000000, 0x4 },
+ [MICROCHIP_PFSOC_FABRIC_FIC3] = { 0x40000000, 0x20000000 },
[MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
[MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
[MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
@@ -292,11 +304,21 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev,
Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0,
memmap[MICROCHIP_PFSOC_SYSREG].base);
+ /* AXISW */
+ create_unimplemented_device("microchip.pfsoc.axisw",
+ memmap[MICROCHIP_PFSOC_AXISW].base,
+ memmap[MICROCHIP_PFSOC_AXISW].size);
+
/* MPUCFG */
create_unimplemented_device("microchip.pfsoc.mpucfg",
memmap[MICROCHIP_PFSOC_MPUCFG].base,
memmap[MICROCHIP_PFSOC_MPUCFG].size);
+ /* FMETER */
+ create_unimplemented_device("microchip.pfsoc.fmeter",
+ memmap[MICROCHIP_PFSOC_FMETER].base,
+ memmap[MICROCHIP_PFSOC_FMETER].size);
+
/* DDR SGMII PHY */
sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0,
@@ -336,6 +358,23 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev,
Error **errp)
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
serial_hd(4));
+ /* Watchdogs */
+ create_unimplemented_device("microchip.pfsoc.watchdog0",
+ memmap[MICROCHIP_PFSOC_WDOG0].base,
+ memmap[MICROCHIP_PFSOC_WDOG0].size);
+ create_unimplemented_device("microchip.pfsoc.watchdog1",
+ memmap[MICROCHIP_PFSOC_WDOG1].base,
+ memmap[MICROCHIP_PFSOC_WDOG1].size);
+ create_unimplemented_device("microchip.pfsoc.watchdog2",
+ memmap[MICROCHIP_PFSOC_WDOG2].base,
+ memmap[MICROCHIP_PFSOC_WDOG2].size);
+ create_unimplemented_device("microchip.pfsoc.watchdog3",
+ memmap[MICROCHIP_PFSOC_WDOG3].base,
+ memmap[MICROCHIP_PFSOC_WDOG3].size);
+ create_unimplemented_device("microchip.pfsoc.watchdog4",
+ memmap[MICROCHIP_PFSOC_WDOG4].base,
+ memmap[MICROCHIP_PFSOC_WDOG4].size);
+
/* SPI */
create_unimplemented_device("microchip.pfsoc.spi0",
memmap[MICROCHIP_PFSOC_SPI0].base,
@@ -344,11 +383,27 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev,
Error **errp)
memmap[MICROCHIP_PFSOC_SPI1].base,
memmap[MICROCHIP_PFSOC_SPI1].size);
- /* I2C1 */
+ /* I2C */
+ create_unimplemented_device("microchip.pfsoc.i2c0",
+ memmap[MICROCHIP_PFSOC_I2C0].base,
+ memmap[MICROCHIP_PFSOC_I2C0].size);
create_unimplemented_device("microchip.pfsoc.i2c1",
memmap[MICROCHIP_PFSOC_I2C1].base,
memmap[MICROCHIP_PFSOC_I2C1].size);
+ /* CAN */
+ create_unimplemented_device("microchip.pfsoc.can0",
+ memmap[MICROCHIP_PFSOC_CAN0].base,
+ memmap[MICROCHIP_PFSOC_CAN0].size);
+ create_unimplemented_device("microchip.pfsoc.can1",
+ memmap[MICROCHIP_PFSOC_CAN1].base,
+ memmap[MICROCHIP_PFSOC_CAN1].size);
+
+ /* USB */
+ create_unimplemented_device("microchip.pfsoc.usb",
+ memmap[MICROCHIP_PFSOC_USB].base,
+ memmap[MICROCHIP_PFSOC_USB].size);
+
/* GEMs */
nd = &nd_table[0];
@@ -402,10 +457,10 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev,
Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
memmap[MICROCHIP_PFSOC_IOSCB].base);
- /* eMMC/SD mux */
- create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
- memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
- memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
+ /* FPGA Fabric */
+ create_unimplemented_device("microchip.pfsoc.fabricfic3",
+ memmap[MICROCHIP_PFSOC_FABRIC_FIC3].base,
+ memmap[MICROCHIP_PFSOC_FABRIC_FIC3].size);
/* QSPI Flash */
memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
--
2.37.2
- [PULL 17/44] target/riscv: rvv: Add mask agnostic for vx instructions, (continued)
- [PULL 17/44] target/riscv: rvv: Add mask agnostic for vx instructions, Alistair Francis, 2022/09/07
- [PULL 19/44] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions, Alistair Francis, 2022/09/07
- [PULL 18/44] target/riscv: rvv: Add mask agnostic for vector integer shift instructions, Alistair Francis, 2022/09/07
- [PULL 21/44] target/riscv: rvv: Add mask agnostic for vector floating-point instructions, Alistair Francis, 2022/09/07
- [PULL 20/44] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions, Alistair Francis, 2022/09/07
- [PULL 22/44] target/riscv: rvv: Add mask agnostic for vector mask instructions, Alistair Francis, 2022/09/07
- [PULL 23/44] target/riscv: rvv: Add mask agnostic for vector permutation instructions, Alistair Francis, 2022/09/07
- [PULL 25/44] target/riscv: Add Zihintpause support, Alistair Francis, 2022/09/07
- [PULL 24/44] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior, Alistair Francis, 2022/09/07
- [PULL 26/44] hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec(), Alistair Francis, 2022/09/07
- [PULL 29/44] hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals,
Alistair Francis <=
- [PULL 28/44] hw/riscv: opentitan: bump opentitan version, Alistair Francis, 2022/09/07
- [PULL 31/44] hw/riscv: virt: fix uart node name, Alistair Francis, 2022/09/07
- [PULL 35/44] target/riscv: Add xicondops in ISA entry, Alistair Francis, 2022/09/07
- [PULL 43/44] hw/riscv: virt: Add PMU DT node to the device tree, Alistair Francis, 2022/09/07
- [PULL 36/44] target/riscv: Use official extension names for AIA CSRs, Alistair Francis, 2022/09/07
- [PULL 34/44] hw/core: fix platform bus node name, Alistair Francis, 2022/09/07
- [PULL 27/44] target/riscv: Fix priority of csr related check in riscv_csrrw_check, Alistair Francis, 2022/09/07
- [PULL 30/44] target/riscv: Remove additional priv version check for mcountinhibit, Alistair Francis, 2022/09/07
- [PULL 32/44] hw/riscv: virt: fix the plic's address cells, Alistair Francis, 2022/09/07
- [PULL 41/44] target/riscv: Simplify counter predicate function, Alistair Francis, 2022/09/07