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[PATCH 17/42] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS
From: |
Bernhard Beschow |
Subject: |
[PATCH 17/42] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS |
Date: |
Thu, 1 Sep 2022 18:25:48 +0200 |
PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise
inconsistencies can occur.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
hw/isa/piix3.c | 8 ++++----
include/hw/southbridge/piix.h | 5 ++---
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index a4a5f33d6e..ae1df8e73e 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -51,7 +51,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3,
int pirq, int level)
uint64_t mask;
pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
- if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+ if (pic_irq >= ISA_NUM_IRQS) {
return;
}
@@ -65,7 +65,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq,
int level)
int pic_irq;
pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
- if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+ if (pic_irq >= ISA_NUM_IRQS) {
return;
}
@@ -97,7 +97,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque,
int pin)
int irq = piix3->dev.config[PIIX_PIRQCA + pin];
PCIINTxRoute route;
- if (irq < PIIX_NUM_PIC_IRQS) {
+ if (irq < ISA_NUM_IRQS) {
route.mode = PCI_INTX_ENABLED;
route.irq = irq;
} else {
@@ -129,7 +129,7 @@ static void piix3_write_config(PCIDevice *dev,
pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
piix3_update_irq_levels(piix3);
- for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
+ for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) {
piix3_set_irq_pic(piix3, pic_irq);
}
}
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index df3e0084c5..ae3b49fe93 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -32,7 +32,6 @@
*/
#define PIIX_RCR_IOPORT 0xcf9
-#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
struct PIIXState {
@@ -44,10 +43,10 @@ struct PIIXState {
* So one PIC level is tracked by PIIX_NUM_PIRQS bits.
*
* PIRQ is mapped to PIC pins, we track it by
- * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
+ * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with
* pic_irq * PIIX_NUM_PIRQS + pirq
*/
-#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
+#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64
#error "unable to encode pic state in 64bit in pic_levels."
#endif
uint64_t pic_levels;
--
2.37.3
- [PATCH 09/42] hw/isa/piix3: Create IDE controller in host device, (continued)
- [PATCH 09/42] hw/isa/piix3: Create IDE controller in host device, Bernhard Beschow, 2022/09/01
- [PATCH 12/42] hw/isa/piix3: Remove unused include, Bernhard Beschow, 2022/09/01
- [PATCH 14/42] hw/isa/piix3: Modernize reset handling, Bernhard Beschow, 2022/09/01
- [PATCH 13/42] hw/isa/piix3: Add size constraints to rcr_ops, Bernhard Beschow, 2022/09/01
- [PATCH 16/42] hw/isa/piix3: Allow board to provide PCI interrupt routes, Bernhard Beschow, 2022/09/01
- [PATCH 15/42] hw/isa/piix3: Prefer pci_address_space() over get_system_memory(), Bernhard Beschow, 2022/09/01
- [PATCH 17/42] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS,
Bernhard Beschow <=
- [PATCH 20/42] hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_", Bernhard Beschow, 2022/09/01
- [PATCH 18/42] hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4, Bernhard Beschow, 2022/09/01
- [PATCH 23/42] meson: Fix dependencies of piix4 southbridge, Bernhard Beschow, 2022/09/01
- [PATCH 19/42] hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4, Bernhard Beschow, 2022/09/01
- [PATCH 22/42] hw/mips/malta: Reuse dev variable, Bernhard Beschow, 2022/09/01
- [PATCH 32/42] hw/isa/piix4: Rename wrongly named method, Bernhard Beschow, 2022/09/01
- [PATCH 31/42] hw/isa/piix4: Rename reset control operations to match PIIX3, Bernhard Beschow, 2022/09/01
- [PATCH 24/42] hw/isa/piix4: Add missing initialization, Bernhard Beschow, 2022/09/01