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[PATCH 16/42] hw/isa/piix3: Allow board to provide PCI interrupt routes
From: |
Bernhard Beschow |
Subject: |
[PATCH 16/42] hw/isa/piix3: Allow board to provide PCI interrupt routes |
Date: |
Thu, 1 Sep 2022 18:25:47 +0200 |
PIIX3 initializes the PIRQx route control registers to the default
values as described in the 82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4)
April 1997 manual. PIIX4, however, initializes the routes according to
the Malta™ User’s Manual, ch 6.6, which are IRQs 10 and 11. In order to
allow the reset methods to be consolidated, allow board code to specify
the routes.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
hw/isa/piix3.c | 12 ++++++++----
include/hw/southbridge/piix.h | 1 +
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index f8fcd47e24..a4a5f33d6e 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -167,10 +167,10 @@ static void piix3_reset(DeviceState *dev)
pci_conf[0x4c] = 0x4d;
pci_conf[0x4e] = 0x03;
pci_conf[0x4f] = 0x00;
- pci_conf[0x60] = 0x80;
- pci_conf[0x61] = 0x80;
- pci_conf[0x62] = 0x80;
- pci_conf[0x63] = 0x80;
+ pci_conf[PIIX_PIRQCA] = d->pci_irq_reset_mappings[0];
+ pci_conf[PIIX_PIRQCB] = d->pci_irq_reset_mappings[1];
+ pci_conf[PIIX_PIRQCC] = d->pci_irq_reset_mappings[2];
+ pci_conf[PIIX_PIRQCD] = d->pci_irq_reset_mappings[3];
pci_conf[0x69] = 0x02;
pci_conf[0x70] = 0x80;
pci_conf[0x76] = 0x0c;
@@ -382,6 +382,10 @@ static void pci_piix3_init(Object *obj)
static Property pci_piix3_props[] = {
DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0),
+ DEFINE_PROP_UINT8("pirqa", PIIX3State, pci_irq_reset_mappings[0], 0x80),
+ DEFINE_PROP_UINT8("pirqb", PIIX3State, pci_irq_reset_mappings[1], 0x80),
+ DEFINE_PROP_UINT8("pirqc", PIIX3State, pci_irq_reset_mappings[2], 0x80),
+ DEFINE_PROP_UINT8("pirqd", PIIX3State, pci_irq_reset_mappings[3], 0x80),
DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true),
DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true),
DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false),
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 1f22eb1444..df3e0084c5 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -54,6 +54,7 @@ struct PIIXState {
/* This member isn't used. Just for save/load compatibility */
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
+ uint8_t pci_irq_reset_mappings[PIIX_NUM_PIRQS];
ISAPICState pic;
RTCState rtc;
--
2.37.3
- [PATCH 10/42] hw/isa/piix3: Wire up ACPI interrupt internally, (continued)
- [PATCH 10/42] hw/isa/piix3: Wire up ACPI interrupt internally, Bernhard Beschow, 2022/09/01
- [PATCH 11/42] hw/isa/piix3: Remove extra ';' outside of functions, Bernhard Beschow, 2022/09/01
- [PATCH 09/42] hw/isa/piix3: Create IDE controller in host device, Bernhard Beschow, 2022/09/01
- [PATCH 12/42] hw/isa/piix3: Remove unused include, Bernhard Beschow, 2022/09/01
- [PATCH 14/42] hw/isa/piix3: Modernize reset handling, Bernhard Beschow, 2022/09/01
- [PATCH 13/42] hw/isa/piix3: Add size constraints to rcr_ops, Bernhard Beschow, 2022/09/01
- [PATCH 16/42] hw/isa/piix3: Allow board to provide PCI interrupt routes,
Bernhard Beschow <=
- [PATCH 15/42] hw/isa/piix3: Prefer pci_address_space() over get_system_memory(), Bernhard Beschow, 2022/09/01
- [PATCH 17/42] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS, Bernhard Beschow, 2022/09/01
- [PATCH 20/42] hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_", Bernhard Beschow, 2022/09/01
- [PATCH 18/42] hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4, Bernhard Beschow, 2022/09/01
- [PATCH 23/42] meson: Fix dependencies of piix4 southbridge, Bernhard Beschow, 2022/09/01
- [PATCH 19/42] hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4, Bernhard Beschow, 2022/09/01
- [PATCH 22/42] hw/mips/malta: Reuse dev variable, Bernhard Beschow, 2022/09/01
- [PATCH 32/42] hw/isa/piix4: Rename wrongly named method, Bernhard Beschow, 2022/09/01