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[PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 mo
From: |
Peter Maydell |
Subject: |
[PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 modes |
Date: |
Mon, 9 May 2022 12:58:27 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
during arm_cpu_realizefn.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 22 +++++++++++++---------
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 01176b2569f..7995ff27126 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1801,11 +1801,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
*/
unset_feature(env, ARM_FEATURE_EL3);
- /* Disable the security extension feature bits in the processor feature
- * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
+ /*
+ * Disable the security extension feature bits in the processor
+ * feature registers as well.
*/
- cpu->isar.id_pfr1 &= ~0xf0;
- cpu->isar.id_aa64pfr0 &= ~0xf000;
+ cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY,
0);
+ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
+ ID_AA64PFR0, EL3, 0);
}
if (!cpu->has_el2) {
@@ -1836,12 +1838,14 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
}
if (!arm_feature(env, ARM_FEATURE_EL2)) {
- /* Disable the hypervisor feature bits in the processor feature
- * registers if we don't have EL2. These are id_pfr1[15:12] and
- * id_aa64pfr0_el1[11:8].
+ /*
+ * Disable the hypervisor feature bits in the processor feature
+ * registers if we don't have EL2.
*/
- cpu->isar.id_aa64pfr0 &= ~0xf00;
- cpu->isar.id_pfr1 &= ~0xf000;
+ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
+ ID_AA64PFR0, EL2, 0);
+ cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
+ ID_PFR1, VIRTUALIZATION, 0);
}
#ifndef CONFIG_USER_ONLY
--
2.25.1
- [PULL 00/32] target-arm queue, Peter Maydell, 2022/05/09
- [PULL 01/32] MAINTAINERS/.mailmap: update email for Leif Lindholm, Peter Maydell, 2022/05/09
- [PULL 03/32] target/arm: Drop EL3 no EL2 fallbacks, Peter Maydell, 2022/05/09
- [PULL 04/32] target/arm: Merge zcr reginfo, Peter Maydell, 2022/05/09
- [PULL 05/32] target/arm: Adjust definition of CONTEXTIDR_EL2, Peter Maydell, 2022/05/09
- [PULL 02/32] target/arm: Handle cpreg registration for missing EL, Peter Maydell, 2022/05/09
- [PULL 06/32] target/arm: Move cortex impdef sysregs to cpu_tcg.c, Peter Maydell, 2022/05/09
- [PULL 09/32] target/arm: Split out aa32_max_features, Peter Maydell, 2022/05/09
- [PULL 10/32] target/arm: Annotate arm_max_initfn with FEAT identifiers, Peter Maydell, 2022/05/09
- [PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 modes,
Peter Maydell <=
- [PULL 12/32] target/arm: Enable FEAT_Debugv8p2 for -cpu max, Peter Maydell, 2022/05/09
- [PULL 07/32] target/arm: Update qemu-system-arm -cpu max to cortex-a57, Peter Maydell, 2022/05/09
- [PULL 08/32] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max, Peter Maydell, 2022/05/09
- [PULL 15/32] target/arm: Enable SCR and HCR bits for RAS, Peter Maydell, 2022/05/09
- [PULL 17/32] target/arm: Implement ESB instruction, Peter Maydell, 2022/05/09
- [PULL 16/32] target/arm: Implement virtual SError exceptions, Peter Maydell, 2022/05/09
- [PULL 19/32] target/arm: Enable FEAT_IESB for -cpu max, Peter Maydell, 2022/05/09
- [PULL 20/32] target/arm: Enable FEAT_CSV2 for -cpu max, Peter Maydell, 2022/05/09
- [PULL 18/32] target/arm: Enable FEAT_RAS for -cpu max, Peter Maydell, 2022/05/09
- [PULL 21/32] target/arm: Enable FEAT_CSV2_2 for -cpu max, Peter Maydell, 2022/05/09