[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 7/8] ppc/ppc405: Introduce a store helper for SPR_40x_PID
From: |
Cédric Le Goater |
Subject: |
[PATCH 7/8] ppc/ppc405: Introduce a store helper for SPR_40x_PID |
Date: |
Wed, 22 Dec 2021 07:40:24 +0100 |
The PID SPR of the 405 CPU contains the translation ID of the TLB
which is a 8-bit field. Enforce the mask with a store helper.
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/spr_tcg.h | 1 +
target/ppc/cpu_init.c | 2 +-
target/ppc/translate.c | 8 ++++++++
3 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h
index 64cf5302cb86..89ff111724dc 100644
--- a/target/ppc/spr_tcg.h
+++ b/target/ppc/spr_tcg.h
@@ -89,6 +89,7 @@ void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int
gprn);
void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn);
+void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn);
void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn);
void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn);
void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn);
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index b5e2fde9ec4d..9ef9a1a5ddd5 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -1454,7 +1454,7 @@ static void register_405_sprs(CPUPPCState *env)
/* MMU */
spr_register(env, SPR_40x_PID, "PID",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_40x_pid,
0x00000000);
spr_register(env, SPR_4xx_CCR0, "CCR0",
SPR_NOACCESS, SPR_NOACCESS,
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index eb45f679d34f..cb8ab4d67635 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -890,6 +890,14 @@ void spr_write_40x_tsr(DisasContext *ctx, int sprn, int
gprn)
gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]);
}
+void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF);
+ gen_store_spr(SPR_40x_PID, t0);
+ tcg_temp_free(t0);
+}
+
void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
{
gen_icount_io_start(ctx);
--
2.31.1
- [PATCH 1/8] target/ppc: Print out literal exception names in logs, (continued)
- [PATCH 1/8] target/ppc: Print out literal exception names in logs, Cédric Le Goater, 2021/12/22
- [PATCH 4/8] ppc/ppc405: Restore TCR and STR write handlers, Cédric Le Goater, 2021/12/22
- [PATCH 5/8] ppc/ppc405: Rework ppc_40x_timers_init() to use a PowerPCCPU, Cédric Le Goater, 2021/12/22
- [PATCH 6/8] ppc/ppc405: Fix timer initialization, Cédric Le Goater, 2021/12/22
- [PATCH 7/8] ppc/ppc405: Introduce a store helper for SPR_40x_PID,
Cédric Le Goater <=
- [PATCH 2/8] ppc/ppc4xx: Convert printfs(), Cédric Le Goater, 2021/12/22
- [PATCH 8/8] ppc/ppc405: Dump specific registers, Cédric Le Goater, 2021/12/22