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[PULL 20/31] tcg/loongarch64: Implement setcond ops
From: |
Richard Henderson |
Subject: |
[PULL 20/31] tcg/loongarch64: Implement setcond ops |
Date: |
Tue, 21 Dec 2021 08:47:26 -0800 |
From: WANG Xuerui <git@xen0n.name>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211221054105.178795-21-git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 69 ++++++++++++++++++++++++++++
2 files changed, 70 insertions(+)
diff --git a/tcg/loongarch64/tcg-target-con-set.h
b/tcg/loongarch64/tcg-target-con-set.h
index 367689c2e2..a2ec61237e 100644
--- a/tcg/loongarch64/tcg-target-con-set.h
+++ b/tcg/loongarch64/tcg-target-con-set.h
@@ -22,6 +22,7 @@ C_O1_I2(r, r, ri)
C_O1_I2(r, r, rI)
C_O1_I2(r, r, rU)
C_O1_I2(r, r, rW)
+C_O1_I2(r, r, rZ)
C_O1_I2(r, 0, rZ)
C_O1_I2(r, rZ, rN)
C_O1_I2(r, rZ, rZ)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index aedfc0df84..23c151f473 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -434,6 +434,66 @@ static void tcg_out_clzctz(TCGContext *s, LoongArchInsn
opc,
tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0);
}
+static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
+ TCGReg arg1, TCGReg arg2, bool c2)
+{
+ TCGReg tmp;
+
+ if (c2) {
+ tcg_debug_assert(arg2 == 0);
+ }
+
+ switch (cond) {
+ case TCG_COND_EQ:
+ if (c2) {
+ tmp = arg1;
+ } else {
+ tcg_out_opc_sub_d(s, ret, arg1, arg2);
+ tmp = ret;
+ }
+ tcg_out_opc_sltui(s, ret, tmp, 1);
+ break;
+ case TCG_COND_NE:
+ if (c2) {
+ tmp = arg1;
+ } else {
+ tcg_out_opc_sub_d(s, ret, arg1, arg2);
+ tmp = ret;
+ }
+ tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, tmp);
+ break;
+ case TCG_COND_LT:
+ tcg_out_opc_slt(s, ret, arg1, arg2);
+ break;
+ case TCG_COND_GE:
+ tcg_out_opc_slt(s, ret, arg1, arg2);
+ tcg_out_opc_xori(s, ret, ret, 1);
+ break;
+ case TCG_COND_LE:
+ tcg_out_setcond(s, TCG_COND_GE, ret, arg2, arg1, false);
+ break;
+ case TCG_COND_GT:
+ tcg_out_setcond(s, TCG_COND_LT, ret, arg2, arg1, false);
+ break;
+ case TCG_COND_LTU:
+ tcg_out_opc_sltu(s, ret, arg1, arg2);
+ break;
+ case TCG_COND_GEU:
+ tcg_out_opc_sltu(s, ret, arg1, arg2);
+ tcg_out_opc_xori(s, ret, ret, 1);
+ break;
+ case TCG_COND_LEU:
+ tcg_out_setcond(s, TCG_COND_GEU, ret, arg2, arg1, false);
+ break;
+ case TCG_COND_GTU:
+ tcg_out_setcond(s, TCG_COND_LTU, ret, arg2, arg1, false);
+ break;
+ default:
+ g_assert_not_reached();
+ break;
+ }
+}
+
/*
* Branch helpers
*/
@@ -815,6 +875,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_opc_mod_du(s, a0, a1, a2);
break;
+ case INDEX_op_setcond_i32:
+ case INDEX_op_setcond_i64:
+ tcg_out_setcond(s, args[3], a0, a1, a2, c2);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
default:
@@ -901,6 +966,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_ctz_i64:
return C_O1_I2(r, r, rW);
+ case INDEX_op_setcond_i32:
+ case INDEX_op_setcond_i64:
+ return C_O1_I2(r, r, rZ);
+
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
/* Must deposit into the same register as input */
--
2.25.1
- [PULL 14/31] tcg/loongarch64: Implement bswap{16,32,64} ops, (continued)
- [PULL 14/31] tcg/loongarch64: Implement bswap{16,32,64} ops, Richard Henderson, 2021/12/21
- [PULL 13/31] tcg/loongarch64: Implement deposit/extract ops, Richard Henderson, 2021/12/21
- [PULL 12/31] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops, Richard Henderson, 2021/12/21
- [PULL 15/31] tcg/loongarch64: Implement clz/ctz ops, Richard Henderson, 2021/12/21
- [PULL 16/31] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops, Richard Henderson, 2021/12/21
- [PULL 17/31] tcg/loongarch64: Implement add/sub ops, Richard Henderson, 2021/12/21
- [PULL 18/31] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops, Richard Henderson, 2021/12/21
- [PULL 19/31] tcg/loongarch64: Implement br/brcond ops, Richard Henderson, 2021/12/21
- [PULL 11/31] tcg/loongarch64: Implement sign-/zero-extension ops, Richard Henderson, 2021/12/21
- [PULL 23/31] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops, Richard Henderson, 2021/12/21
- [PULL 20/31] tcg/loongarch64: Implement setcond ops,
Richard Henderson <=
- [PULL 26/31] tcg/loongarch64: Implement tcg_target_init, Richard Henderson, 2021/12/21
- [PULL 08/31] tcg/loongarch64: Implement the memory barrier op, Richard Henderson, 2021/12/21
- [PULL 22/31] tcg/loongarch64: Implement simple load/store ops, Richard Henderson, 2021/12/21
- [PULL 10/31] tcg/loongarch64: Implement goto_ptr, Richard Henderson, 2021/12/21
- [PULL 24/31] tcg/loongarch64: Implement tcg_target_qemu_prologue, Richard Henderson, 2021/12/21
- [PULL 29/31] linux-user: Implement CPU-specific signal handler for loongarch64 hosts, Richard Henderson, 2021/12/21
- [PULL 28/31] common-user: Add safe syscall handling for loongarch64 hosts, Richard Henderson, 2021/12/21
- [PULL 30/31] configure, meson.build: Mark support for loongarch64 hosts, Richard Henderson, 2021/12/21
- [PULL 31/31] tests/docker: Add gentoo-loongarch64-cross image and run cross builds in GitLab, Richard Henderson, 2021/12/21
- [PULL 21/31] tcg/loongarch64: Implement tcg_out_call, Richard Henderson, 2021/12/21