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[PULL 79/88] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
From: |
Alistair Francis |
Subject: |
[PULL 79/88] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 |
Date: |
Mon, 20 Dec 2021 14:56:56 +1000 |
From: Frank Chang <frank.chang@sifive.com>
Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction.
vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-72-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 952768f8de..d7c6bc9af2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -78,7 +78,7 @@
@r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
@r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
-@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
+@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd
@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@@ -671,7 +671,7 @@ vsext_vf2 010010 . ..... 00111 010 ..... 1010111
@r2_vm
vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
-vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
+vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
# *** RV32 Zba Standard Extension ***
--
2.31.1
- [PULL 64/88] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, (continued)
- [PULL 64/88] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, Alistair Francis, 2021/12/20
- [PULL 71/88] target/riscv: add "set round to odd" rounding mode helper function, Alistair Francis, 2021/12/20
- [PULL 66/88] target/riscv: rvv-1.0: remove integer extract instruction, Alistair Francis, 2021/12/20
- [PULL 62/88] target/riscv: rvv-1.0: widening floating-point reduction instructions, Alistair Francis, 2021/12/20
- [PULL 88/88] hw/riscv: Use load address rather than entry point for fw_dynamic next_addr, Alistair Francis, 2021/12/20
- [PULL 82/88] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, Alistair Francis, 2021/12/20
- [PULL 69/88] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, Alistair Francis, 2021/12/20
- [PULL 72/88] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, Alistair Francis, 2021/12/20
- [PULL 59/88] target/riscv: rvv-1.0: floating-point slide instructions, Alistair Francis, 2021/12/20
- [PULL 76/88] target/riscv: gdb: support vector registers for rv64 & rv32, Alistair Francis, 2021/12/20
- [PULL 79/88] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11,
Alistair Francis <=
- [PULL 80/88] target/riscv: rvv-1.0: add vsetivli instruction, Alistair Francis, 2021/12/20
- [PULL 68/88] target/riscv: introduce floating-point rounding mode enum, Alistair Francis, 2021/12/20
- [PULL 81/88] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(), Alistair Francis, 2021/12/20
- [PULL 70/88] target/riscv: rvv-1.0: widening floating-point/integer type-convert, Alistair Francis, 2021/12/20
- [PULL 83/88] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm, Alistair Francis, 2021/12/20
- Re: [PULL 00/88] riscv-to-apply queue, Richard Henderson, 2021/12/20