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[PULL 71/88] target/riscv: add "set round to odd" rounding mode helper f
From: |
Alistair Francis |
Subject: |
[PULL 71/88] target/riscv: add "set round to odd" rounding mode helper function |
Date: |
Mon, 20 Dec 2021 14:56:48 +1000 |
From: Frank Chang <frank.chang@sifive.com>
helper_set_rounding_mode() is responsible for SIGILL, and "round to odd"
should be an interface private to translation, so add a new independent
helper_set_rod_rounding_mode().
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-64-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 1 +
target/riscv/internals.h | 1 +
target/riscv/fpu_helper.c | 5 +++++
target/riscv/translate.c | 7 +++++++
4 files changed, 14 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 53cf88cd40..606bf72d5c 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -3,6 +3,7 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32)
/* Floating Point - rounding mode */
DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32)
+DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env)
/* Floating Point - fused */
DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index db105d4d64..065e8162a2 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -43,6 +43,7 @@ enum {
RISCV_FRM_RUP = 3, /* Round Up */
RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */
RISCV_FRM_DYN = 7, /* Dynamic rounding mode */
+ RISCV_FRM_ROD = 8, /* Round to Odd */
};
static inline uint64_t nanbox_s(float32 f)
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index dec39d4a9e..4a5982d594 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -81,6 +81,11 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t
rm)
set_float_rounding_mode(softrm, &env->fp_status);
}
+void helper_set_rod_rounding_mode(CPURISCVState *env)
+{
+ set_float_rounding_mode(float_round_to_odd, &env->fp_status);
+}
+
static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2,
uint64_t rs3, int flags)
{
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3688e80d03..b4df21bda3 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -30,6 +30,7 @@
#include "exec/log.h"
#include "instmap.h"
+#include "internals.h"
/* global register indices */
static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
@@ -403,6 +404,12 @@ static void gen_set_rm(DisasContext *ctx, int rm)
return;
}
ctx->frm = rm;
+
+ if (rm == RISCV_FRM_ROD) {
+ gen_helper_set_rod_rounding_mode(cpu_env);
+ return;
+ }
+
gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
}
--
2.31.1
- [PULL 55/88] target/riscv: rvv-1.0: integer comparison instructions, (continued)
- [PULL 55/88] target/riscv: rvv-1.0: integer comparison instructions, Alistair Francis, 2021/12/20
- [PULL 61/88] target/riscv: rvv-1.0: single-width floating-point reduction, Alistair Francis, 2021/12/20
- [PULL 65/88] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, Alistair Francis, 2021/12/20
- [PULL 86/88] riscv: Set 5.4 as minimum kernel version for riscv32, Alistair Francis, 2021/12/20
- [PULL 73/88] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, Alistair Francis, 2021/12/20
- [PULL 77/88] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, Alistair Francis, 2021/12/20
- [PULL 63/88] target/riscv: rvv-1.0: single-width scaling shift instructions, Alistair Francis, 2021/12/20
- [PULL 74/88] target/riscv: rvv-1.0: implement vstart CSR, Alistair Francis, 2021/12/20
- [PULL 58/88] target/riscv: rvv-1.0: slide instructions, Alistair Francis, 2021/12/20
- [PULL 64/88] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, Alistair Francis, 2021/12/20
- [PULL 71/88] target/riscv: add "set round to odd" rounding mode helper function,
Alistair Francis <=
- [PULL 66/88] target/riscv: rvv-1.0: remove integer extract instruction, Alistair Francis, 2021/12/20
- [PULL 62/88] target/riscv: rvv-1.0: widening floating-point reduction instructions, Alistair Francis, 2021/12/20
- [PULL 88/88] hw/riscv: Use load address rather than entry point for fw_dynamic next_addr, Alistair Francis, 2021/12/20
- [PULL 82/88] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, Alistair Francis, 2021/12/20
- [PULL 69/88] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, Alistair Francis, 2021/12/20
- [PULL 72/88] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, Alistair Francis, 2021/12/20
- [PULL 59/88] target/riscv: rvv-1.0: floating-point slide instructions, Alistair Francis, 2021/12/20
- [PULL 76/88] target/riscv: gdb: support vector registers for rv64 & rv32, Alistair Francis, 2021/12/20
- [PULL 79/88] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, Alistair Francis, 2021/12/20
- [PULL 80/88] target/riscv: rvv-1.0: add vsetivli instruction, Alistair Francis, 2021/12/20