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[PULL 082/102] target/ppc: introduce PMUEventType and PMU overflow timer
From: |
Cédric Le Goater |
Subject: |
[PULL 082/102] target/ppc: introduce PMUEventType and PMU overflow timers |
Date: |
Wed, 15 Dec 2021 18:03:37 +0100 |
From: Daniel Henrique Barboza <danielhb413@gmail.com>
This patch starts an IBM Power8+ compatible PMU implementation by adding
the representation of PMU events that we are going to sample,
PMUEventType. This enum represents a Perf event that is being sampled by
a specific counter 'sprn'. Events that aren't available (i.e. no event
was set in MMCR1) will be of type 'PMU_EVENT_INVALID'. Events that are
inactive due to frozen counter bits state are of type
'PMU_EVENT_INACTIVE'. Other types added in this patch are
PMU_EVENT_CYCLES and PMU_EVENT_INSTRUCTIONS. More types will be added
later on.
Let's also add the required PMU cycle overflow timers. They will be used
to trigger cycle overflows when cycle events are being sampled. This
timer will call cpu_ppc_pmu_timer_cb(), which in turn calls
fire_PMC_interrupt(). Both functions are stubs that will be implemented
later on when EBB support is added.
Two new helper files are created to host this new logic.
cpu_ppc_pmu_init() will init all overflow timers during CPU init time.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 15 ++++++++++
target/ppc/power8-pmu.h | 25 +++++++++++++++++
hw/ppc/spapr_cpu_core.c | 1 +
target/ppc/cpu_init.c | 24 ++++++++++++++++
target/ppc/power8-pmu.c | 62 +++++++++++++++++++++++++++++++++++++++++
target/ppc/meson.build | 1 +
6 files changed, 128 insertions(+)
create mode 100644 target/ppc/power8-pmu.h
create mode 100644 target/ppc/power8-pmu.c
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index c07a8e9f7d4b..39fadca564bb 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -296,6 +296,15 @@ typedef struct ppc_v3_pate_t {
uint64_t dw1;
} ppc_v3_pate_t;
+/* PMU related structs and defines */
+#define PMU_COUNTERS_NUM 6
+typedef enum {
+ PMU_EVENT_INVALID = 0,
+ PMU_EVENT_INACTIVE,
+ PMU_EVENT_CYCLES,
+ PMU_EVENT_INSTRUCTIONS,
+} PMUEventType;
+
/*****************************************************************************/
/* Machine state register bits definition */
#define MSR_SF 63 /* Sixty-four-bit mode hflags */
@@ -1195,6 +1204,12 @@ struct CPUPPCState {
uint32_t tm_vscr;
uint64_t tm_dscr;
uint64_t tm_tar;
+
+ /*
+ * Timers used to fire performance monitor alerts
+ * when counting cycles.
+ */
+ QEMUTimer *pmu_cyc_overflow_timers[PMU_COUNTERS_NUM];
};
#define SET_FIT_PERIOD(a_, b_, c_, d_) \
diff --git a/target/ppc/power8-pmu.h b/target/ppc/power8-pmu.h
new file mode 100644
index 000000000000..49a813a443d7
--- /dev/null
+++ b/target/ppc/power8-pmu.h
@@ -0,0 +1,25 @@
+/*
+ * PMU emulation helpers for TCG IBM POWER chips
+ *
+ * Copyright IBM Corp. 2021
+ *
+ * Authors:
+ * Daniel Henrique Barboza <danielhb413@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef POWER8_PMU
+#define POWER8_PMU
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
+
+void cpu_ppc_pmu_init(CPUPPCState *env);
+
+#endif
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 58e7341cb784..a57ba70a8781 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -20,6 +20,7 @@
#include "target/ppc/kvm_ppc.h"
#include "hw/ppc/ppc.h"
#include "target/ppc/mmu-hash64.h"
+#include "target/ppc/power8-pmu.h"
#include "sysemu/numa.h"
#include "sysemu/reset.h"
#include "sysemu/hw_accel.h"
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index c8e6868389cb..7c47ffd6e19b 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -45,6 +45,7 @@
#include "helper_regs.h"
#include "internal.h"
#include "spr_tcg.h"
+#include "power8-pmu.h"
/* #define PPC_DEBUG_SPR */
/* #define USE_APPLE_GDB */
@@ -6810,6 +6811,20 @@ static void register_power9_mmu_sprs(CPUPPCState *env)
#endif
}
+/*
+ * Initialize PMU counter overflow timers for Power8 and
+ * newer Power chips when using TCG.
+ */
+static void init_tcg_pmu_power8(CPUPPCState *env)
+{
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+ /* Init PMU overflow timers */
+ if (!kvm_enabled()) {
+ cpu_ppc_pmu_init(env);
+ }
+#endif
+}
+
static void init_proc_book3s_common(CPUPPCState *env)
{
register_ne_601_sprs(env);
@@ -7127,6 +7142,9 @@ static void init_proc_POWER8(CPUPPCState *env)
register_sdr1_sprs(env);
register_book3s_207_dbg_sprs(env);
+ /* Common TCG PMU */
+ init_tcg_pmu_power8(env);
+
/* POWER8 Specific Registers */
register_book3s_ids_sprs(env);
register_rmor_sprs(env);
@@ -7321,6 +7339,9 @@ static void init_proc_POWER9(CPUPPCState *env)
init_proc_book3s_common(env);
register_book3s_207_dbg_sprs(env);
+ /* Common TCG PMU */
+ init_tcg_pmu_power8(env);
+
/* POWER8 Specific Registers */
register_book3s_ids_sprs(env);
register_amr_sprs(env);
@@ -7537,6 +7558,9 @@ static void init_proc_POWER10(CPUPPCState *env)
init_proc_book3s_common(env);
register_book3s_207_dbg_sprs(env);
+ /* Common TCG PMU */
+ init_tcg_pmu_power8(env);
+
/* POWER8 Specific Registers */
register_book3s_ids_sprs(env);
register_amr_sprs(env);
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
new file mode 100644
index 000000000000..d443bcb6c6ca
--- /dev/null
+++ b/target/ppc/power8-pmu.c
@@ -0,0 +1,62 @@
+/*
+ * PMU emulation helpers for TCG IBM POWER chips
+ *
+ * Copyright IBM Corp. 2021
+ *
+ * Authors:
+ * Daniel Henrique Barboza <danielhb413@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+
+#include "power8-pmu.h"
+#include "cpu.h"
+#include "helper_regs.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
+#include "hw/ppc/ppc.h"
+
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+
+static void fire_PMC_interrupt(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+
+ if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_EBE)) {
+ return;
+ }
+
+ /* PMC interrupt not implemented yet */
+ return;
+}
+
+static void cpu_ppc_pmu_timer_cb(void *opaque)
+{
+ PowerPCCPU *cpu = opaque;
+
+ fire_PMC_interrupt(cpu);
+}
+
+void cpu_ppc_pmu_init(CPUPPCState *env)
+{
+ PowerPCCPU *cpu = env_archcpu(env);
+ int i, sprn;
+
+ for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) {
+ if (sprn == SPR_POWER_PMC5) {
+ continue;
+ }
+
+ i = sprn - SPR_POWER_PMC1;
+
+ env->pmu_cyc_overflow_timers[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+ &cpu_ppc_pmu_timer_cb,
+ cpu);
+ }
+}
+#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
diff --git a/target/ppc/meson.build b/target/ppc/meson.build
index b85f29570391..a49a8911e069 100644
--- a/target/ppc/meson.build
+++ b/target/ppc/meson.build
@@ -51,6 +51,7 @@ ppc_softmmu_ss.add(when: 'TARGET_PPC64', if_true: files(
'mmu-book3s-v3.c',
'mmu-hash64.c',
'mmu-radix64.c',
+ 'power8-pmu.c',
))
target_arch += {'ppc': ppc_ss}
--
2.31.1
- [PULL 063/102] ppc: Add trace-events for DCR accesses, (continued)
- [PULL 063/102] ppc: Add trace-events for DCR accesses, Cédric Le Goater, 2021/12/15
- [PULL 073/102] ppc/ppc405: Fix bi_pci_enetaddr2 field in U-Boot board information, Cédric Le Goater, 2021/12/15
- [PULL 074/102] ppc/ppc405: Add update of bi_procfreq field, Cédric Le Goater, 2021/12/15
- [PULL 068/102] ppc/ppc405: Remove flash support, Cédric Le Goater, 2021/12/15
- [PULL 067/102] ppc/ppc405: Add some address space definitions, Cédric Le Goater, 2021/12/15
- [PULL 070/102] ppc/ppc405: Introduce ppc405_set_default_bootinfo(), Cédric Le Goater, 2021/12/15
- [PULL 075/102] target/ppc: Fix xs{max, min}[cj]dp to use VSX registers, Cédric Le Goater, 2021/12/15
- [PULL 065/102] ppc/ppc405: Drop flag parameter in ppc405_set_bootinfo(), Cédric Le Goater, 2021/12/15
- [PULL 071/102] ppc/ppc405: Fix boot from kernel, Cédric Le Goater, 2021/12/15
- [PULL 078/102] target/ppc: move xscvqpdp to decodetree, Cédric Le Goater, 2021/12/15
- [PULL 082/102] target/ppc: introduce PMUEventType and PMU overflow timers,
Cédric Le Goater <=
- [PULL 084/102] target/ppc: PMU: update counters on PMCs r/w, Cédric Le Goater, 2021/12/15
- [PULL 086/102] target/ppc: enable PMU counter overflow with cycle events, Cédric Le Goater, 2021/12/15
- [PULL 085/102] target/ppc: PMU: update counters on MMCR1 write, Cédric Le Goater, 2021/12/15
- [PULL 080/102] Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp", Cédric Le Goater, 2021/12/15
- [PULL 072/102] ppc/ppc405: Change default PLL values at reset, Cédric Le Goater, 2021/12/15
- [PULL 077/102] target/ppc: fix xscvqpdp register access, Cédric Le Goater, 2021/12/15
- [PULL 091/102] ppc/pnv: Use the chip class to check the index of PHB3 devices, Cédric Le Goater, 2021/12/15
- [PULL 079/102] target/ppc: Fix e6500 boot, Cédric Le Goater, 2021/12/15
- [PULL 099/102] ppc/pnv: Compute the PHB index from the PHB4 PEC model, Cédric Le Goater, 2021/12/15
- [PULL 097/102] ppc/pnv: Introduce a "chip" property under the PHB4 model, Cédric Le Goater, 2021/12/15