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Re: [PATCH v11 07/10] hvf: arm: Implement PSCI handling
From: |
Peter Maydell |
Subject: |
Re: [PATCH v11 07/10] hvf: arm: Implement PSCI handling |
Date: |
Thu, 16 Sep 2021 13:27:25 +0100 |
On Wed, 15 Sept 2021 at 19:10, Alexander Graf <agraf@csgraf.de> wrote:
>
> We need to handle PSCI calls. Most of the TCG code works for us,
> but we can simplify it to only handle aa64 mode and we need to
> handle SUSPEND differently.
>
> This patch takes the TCG code as template and duplicates it in HVF.
>
> To tell the guest that we support PSCI 0.2 now, update the check in
> arm_cpu_initfn() as well.
>
> Signed-off-by: Alexander Graf <agraf@csgraf.de>
> Reviewed-by: Sergio Lopez <slp@redhat.com>
> + case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
> + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> + /* QEMU reset and shutdown are async requests, but PSCI
> + * mandates that we never return from the reset/shutdown
> + * call, so power the CPU off now so it doesn't execute
> + * anything further.
> + */
QEMU coding standard wants the opening "/*" of a block comment on its
own line.
> @@ -898,14 +1011,29 @@ int hvf_vcpu_exec(CPUState *cpu)
> break;
> case EC_AA64_HVC:
> cpu_synchronize_state(cpu);
> - trace_hvf_unknown_hvf(env->xregs[0]);
> - /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */
> - env->xregs[0] = -1;
> + if ((arm_cpu->psci_conduit != QEMU_PSCI_CONDUIT_HVC) ||
> + !hvf_handle_psci_call(cpu)) {
> + trace_hvf_unknown_hvf(env->xregs[0]);
> + /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns
> -1 */
> + env->xregs[0] = -1;
> + }
> break;
> case EC_AA64_SMC:
> cpu_synchronize_state(cpu);
> - trace_hvf_unknown_smc(env->xregs[0]);
> - hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
> +
> + if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_SMC) {
> + advance_pc = true;
> +
> + if (!hvf_handle_psci_call(cpu)) {
> + trace_hvf_unknown_smc(env->xregs[0]);
> + /* SMCCC 1.3 section 5.2 says every unknown SMCCC call
> returns -1 */
> + env->xregs[0] = -1;
> + }
> + } else {
> + trace_hvf_unknown_smc(env->xregs[0]);
> + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
> + }
We seem to have ended up with an odd asymmetry in the way the
code for HVC and SMC has been structured.
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- [PATCH v11 05/10] arm/hvf: Add a WFI handler, (continued)
- [PATCH v11 05/10] arm/hvf: Add a WFI handler, Alexander Graf, 2021/09/15
- [PATCH v11 06/10] hvf: arm: Implement -cpu host, Alexander Graf, 2021/09/15
- [PATCH v11 09/10] hvf: arm: Add rudimentary PMC support, Alexander Graf, 2021/09/15
- [PATCH v11 08/10] arm: Add Hypervisor.framework build target, Alexander Graf, 2021/09/15
- [PATCH v11 04/10] hvf: Add Apple Silicon support, Alexander Graf, 2021/09/15
- [PATCH v11 07/10] hvf: arm: Implement PSCI handling, Alexander Graf, 2021/09/15
- Re: [PATCH v11 07/10] hvf: arm: Implement PSCI handling,
Peter Maydell <=
- [PATCH v11 10/10] arm: tcg: Adhere to SMCCC 1.3 section 5.2, Alexander Graf, 2021/09/15