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Re: [PULL 10/36] hostmem: Add hostmem-epc as a backend for SGX EPC
From: |
Yang Zhong |
Subject: |
Re: [PULL 10/36] hostmem: Add hostmem-epc as a backend for SGX EPC |
Date: |
Tue, 7 Sep 2021 14:23:52 +0800 |
User-agent: |
Mutt/1.5.21 (2010-09-15) |
On Mon, Sep 06, 2021 at 03:10:33PM +0200, Paolo Bonzini wrote:
> From: Sean Christopherson <sean.j.christopherson@intel.com>
>
> EPC (Enclave Page Cahe) is a specialized type of memory used by Intel
> SGX (Software Guard Extensions). The SDM desribes EPC as:
>
> The Enclave Page Cache (EPC) is the secure storage used to store
> enclave pages when they are a part of an executing enclave. For an
> EPC page, hardware performs additional access control checks to
> restrict access to the page. After the current page access checks
> and translations are performed, the hardware checks that the EPC
> page is accessible to the program currently executing. Generally an
> EPC page is only accessed by the owner of the executing enclave or
> an instruction which is setting up an EPC page.
>
> Because of its unique requirements, Linux manages EPC separately from
> normal memory. Similar to memfd, the device /dev/sgx_vepc can be
> opened to obtain a file descriptor which can in turn be used to mmap()
> EPC memory.
>
> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
> Signed-off-by: Yang Zhong <yang.zhong@intel.com>
>
> v1-->v2:
> - Unified the "share" and "protected" arguments with ram_flags in the
> memory_region_init_ram_from_fd()(Paolo).
Paolo, I justly verified this PULL list and SGX works well. By the way,
please help remove the version review info in the commit message.
Let me list all patches related with version review here(Only from PULL
list), thanks!
[PULL 09/36] memory: Add RAM_PROTECTED flag to skip IOMMU mappings
[PULL 10/36] hostmem: Add hostmem-epc as a backend for SGX EPC
[PULL 11/36] qom: Add memory-backend-epc ObjectOptions support
[PULL 13/36] vl: Add sgx compound properties to expose SGX EPC sections
[PULL 20/36] i386: Update SGX CPUID info according to hardware/KVM/user input
[PULL 35/36] sgx-epc: Add the fill_device_info() callback support
Yang
> Message-Id: <20210719112136.57018-3-yang.zhong@intel.com>
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> backends/hostmem-epc.c | 92 ++++++++++++++++++++++++++++++++++++++++++
> backends/meson.build | 1 +
> 2 files changed, 93 insertions(+)
> create mode 100644 backends/hostmem-epc.c
>
> diff --git a/backends/hostmem-epc.c b/backends/hostmem-epc.c
> new file mode 100644
> index 0000000000..b512a68cb0
> --- /dev/null
> +++ b/backends/hostmem-epc.c
> @@ -0,0 +1,92 @@
> +/*
> + * QEMU host SGX EPC memory backend
> + *
> + * Copyright (C) 2019 Intel Corporation
> + *
> + * Authors:
> + * Sean Christopherson <sean.j.christopherson@intel.com>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +#include <sys/ioctl.h>
> +
> +#include "qemu/osdep.h"
> +#include "qemu-common.h"
> +#include "qom/object_interfaces.h"
> +#include "qapi/error.h"
> +#include "sysemu/hostmem.h"
> +
> +#define TYPE_MEMORY_BACKEND_EPC "memory-backend-epc"
> +
> +#define MEMORY_BACKEND_EPC(obj) \
> + OBJECT_CHECK(HostMemoryBackendEpc, (obj), TYPE_MEMORY_BACKEND_EPC)
> +
> +typedef struct HostMemoryBackendEpc HostMemoryBackendEpc;
> +
> +struct HostMemoryBackendEpc {
> + HostMemoryBackend parent_obj;
> +};
> +
> +static void
> +sgx_epc_backend_memory_alloc(HostMemoryBackend *backend, Error **errp)
> +{
> + uint32_t ram_flags;
> + char *name;
> + int fd;
> +
> + if (!backend->size) {
> + error_setg(errp, "can't create backend with size 0");
> + return;
> + }
> +
> + fd = qemu_open_old("/dev/sgx_vepc", O_RDWR);
> + if (fd < 0) {
> + error_setg_errno(errp, errno,
> + "failed to open /dev/sgx_vepc to alloc SGX EPC");
> + return;
> + }
> +
> + name = object_get_canonical_path(OBJECT(backend));
> + ram_flags = (backend->share ? RAM_SHARED : 0) | RAM_PROTECTED;
> + memory_region_init_ram_from_fd(&backend->mr, OBJECT(backend),
> + name, backend->size, ram_flags,
> + fd, 0, errp);
> + g_free(name);
> +}
> +
> +static void sgx_epc_backend_instance_init(Object *obj)
> +{
> + HostMemoryBackend *m = MEMORY_BACKEND(obj);
> +
> + m->share = true;
> + m->merge = false;
> + m->dump = false;
> +}
> +
> +static void sgx_epc_backend_class_init(ObjectClass *oc, void *data)
> +{
> + HostMemoryBackendClass *bc = MEMORY_BACKEND_CLASS(oc);
> +
> + bc->alloc = sgx_epc_backend_memory_alloc;
> +}
> +
> +static const TypeInfo sgx_epc_backed_info = {
> + .name = TYPE_MEMORY_BACKEND_EPC,
> + .parent = TYPE_MEMORY_BACKEND,
> + .instance_init = sgx_epc_backend_instance_init,
> + .class_init = sgx_epc_backend_class_init,
> + .instance_size = sizeof(HostMemoryBackendEpc),
> +};
> +
> +static void register_types(void)
> +{
> + int fd = qemu_open_old("/dev/sgx_vepc", O_RDWR);
> + if (fd >= 0) {
> + close(fd);
> +
> + type_register_static(&sgx_epc_backed_info);
> + }
> +}
> +
> +type_init(register_types);
> diff --git a/backends/meson.build b/backends/meson.build
> index d4221831fc..46fd16b269 100644
> --- a/backends/meson.build
> +++ b/backends/meson.build
> @@ -16,5 +16,6 @@ softmmu_ss.add(when: ['CONFIG_VHOST_USER',
> 'CONFIG_VIRTIO'], if_true: files('vho
> softmmu_ss.add(when: 'CONFIG_VIRTIO_CRYPTO', if_true:
> files('cryptodev-vhost.c'))
> softmmu_ss.add(when: ['CONFIG_VIRTIO_CRYPTO', 'CONFIG_VHOST_CRYPTO'],
> if_true: files('cryptodev-vhost-user.c'))
> softmmu_ss.add(when: 'CONFIG_GIO', if_true: [files('dbus-vmstate.c'), gio])
> +softmmu_ss.add(when: 'CONFIG_LINUX', if_true: files('hostmem-epc.c'))
>
> subdir('tpm')
> --
> 2.31.1
>
- [PULL 02/36] target/i386: Added VGIF feature, (continued)
- [PULL 02/36] target/i386: Added VGIF feature, Paolo Bonzini, 2021/09/06
- [PULL 04/36] target/i386: Added VGIF V_IRQ masking capability, Paolo Bonzini, 2021/09/06
- [PULL 05/36] target/i386: Added ignore TPR check in ctl_has_irq, Paolo Bonzini, 2021/09/06
- [PULL 06/36] target/i386: Added changed priority check for VIRQ, Paolo Bonzini, 2021/09/06
- [PULL 08/36] configure / meson: Move the GBM handling to meson.build, Paolo Bonzini, 2021/09/06
- [PULL 15/36] i386: Add SGX CPUID leaf FEAT_SGX_12_0_EAX, Paolo Bonzini, 2021/09/06
- [PULL 07/36] target/i386: Added vVMLOAD and vVMSAVE feature, Paolo Bonzini, 2021/09/06
- [PULL 09/36] memory: Add RAM_PROTECTED flag to skip IOMMU mappings, Paolo Bonzini, 2021/09/06
- [PULL 10/36] hostmem: Add hostmem-epc as a backend for SGX EPC, Paolo Bonzini, 2021/09/06
- Re: [PULL 10/36] hostmem: Add hostmem-epc as a backend for SGX EPC,
Yang Zhong <=
- [PULL 12/36] i386: Add 'sgx-epc' device to expose EPC sections to guest, Paolo Bonzini, 2021/09/06
- [PULL 14/36] i386: Add primary SGX CPUID and MSR defines, Paolo Bonzini, 2021/09/06
- [PULL 19/36] i386: Add feature control MSR dependency when SGX is enabled, Paolo Bonzini, 2021/09/06
- [PULL 20/36] i386: Update SGX CPUID info according to hardware/KVM/user input, Paolo Bonzini, 2021/09/06
- [PULL 16/36] i386: Add SGX CPUID leaf FEAT_SGX_12_0_EBX, Paolo Bonzini, 2021/09/06
- [PULL 17/36] i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX, Paolo Bonzini, 2021/09/06
- [PULL 22/36] i386: Propagate SGX CPUID sub-leafs to KVM, Paolo Bonzini, 2021/09/06
- [PULL 24/36] hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordingly, Paolo Bonzini, 2021/09/06
- [PULL 13/36] vl: Add sgx compound properties to expose SGX EPC sections to guest, Paolo Bonzini, 2021/09/06
- [PULL 11/36] qom: Add memory-backend-epc ObjectOptions support, Paolo Bonzini, 2021/09/06