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[PULL 15/36] i386: Add SGX CPUID leaf FEAT_SGX_12_0_EAX
From: |
Paolo Bonzini |
Subject: |
[PULL 15/36] i386: Add SGX CPUID leaf FEAT_SGX_12_0_EAX |
Date: |
Mon, 6 Sep 2021 15:10:38 +0200 |
From: Sean Christopherson <sean.j.christopherson@intel.com>
CPUID leaf 12_0_EAX is an Intel-defined feature bits leaf enumerating
the CPU's SGX capabilities, e.g. supported SGX instruction sets.
Currently there are four enumerated capabilities:
- SGX1 instruction set, i.e. "base" SGX
- SGX2 instruction set for dynamic EPC management
- ENCLV instruction set for VMM oversubscription of EPC
- ENCLS-C instruction set for thread safe variants of ENCLS
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-8-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.c | 20 ++++++++++++++++++++
target/i386/cpu.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 21d2a325ea..2cd1487bae 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -654,6 +654,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
/* missing:
CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
#define TCG_14_0_ECX_FEATURES 0
+#define TCG_SGX_12_0_EAX_FEATURES 0
FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_1_EDX] = {
@@ -1182,6 +1183,25 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.tcg_features = TCG_14_0_ECX_FEATURES,
},
+ [FEAT_SGX_12_0_EAX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ "sgx1", "sgx2", NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = {
+ .eax = 0x12,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_EAX,
+ },
+ .tcg_features = TCG_SGX_12_0_EAX_FEATURES,
+ },
};
typedef struct FeatureMask {
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 5f56849d1f..29e6490ed6 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -577,6 +577,7 @@ typedef enum FeatureWord {
FEAT_VMX_BASIC,
FEAT_VMX_VMFUNC,
FEAT_14_0_ECX,
+ FEAT_SGX_12_0_EAX, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */
FEATURE_WORDS,
} FeatureWord;
--
2.31.1
- [PULL 00/36] (Mostly) x86 changes for 2021-09-06, Paolo Bonzini, 2021/09/06
- [PULL 01/36] target/i386: VMRUN and VMLOAD canonicalizations, Paolo Bonzini, 2021/09/06
- [PULL 03/36] target/i386: Moved int_ctl into CPUX86State structure, Paolo Bonzini, 2021/09/06
- [PULL 02/36] target/i386: Added VGIF feature, Paolo Bonzini, 2021/09/06
- [PULL 04/36] target/i386: Added VGIF V_IRQ masking capability, Paolo Bonzini, 2021/09/06
- [PULL 05/36] target/i386: Added ignore TPR check in ctl_has_irq, Paolo Bonzini, 2021/09/06
- [PULL 06/36] target/i386: Added changed priority check for VIRQ, Paolo Bonzini, 2021/09/06
- [PULL 08/36] configure / meson: Move the GBM handling to meson.build, Paolo Bonzini, 2021/09/06
- [PULL 15/36] i386: Add SGX CPUID leaf FEAT_SGX_12_0_EAX,
Paolo Bonzini <=
- [PULL 07/36] target/i386: Added vVMLOAD and vVMSAVE feature, Paolo Bonzini, 2021/09/06
- [PULL 09/36] memory: Add RAM_PROTECTED flag to skip IOMMU mappings, Paolo Bonzini, 2021/09/06
- [PULL 10/36] hostmem: Add hostmem-epc as a backend for SGX EPC, Paolo Bonzini, 2021/09/06
- [PULL 12/36] i386: Add 'sgx-epc' device to expose EPC sections to guest, Paolo Bonzini, 2021/09/06
- [PULL 14/36] i386: Add primary SGX CPUID and MSR defines, Paolo Bonzini, 2021/09/06
- [PULL 19/36] i386: Add feature control MSR dependency when SGX is enabled, Paolo Bonzini, 2021/09/06
- [PULL 20/36] i386: Update SGX CPUID info according to hardware/KVM/user input, Paolo Bonzini, 2021/09/06
- [PULL 16/36] i386: Add SGX CPUID leaf FEAT_SGX_12_0_EBX, Paolo Bonzini, 2021/09/06
- [PULL 17/36] i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX, Paolo Bonzini, 2021/09/06