[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 111/114] target/arm: Implement aarch32 VSUDOT, VUSDOT
From: |
Peter Maydell |
Subject: |
[PULL 111/114] target/arm: Implement aarch32 VSUDOT, VUSDOT |
Date: |
Tue, 25 May 2021 16:07:33 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-90-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 5 +++++
target/arm/neon-shared.decode | 6 ++++++
target/arm/translate-neon.c | 27 +++++++++++++++++++++++++++
3 files changed, 38 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 8ecb2a1c89e..04f8be35bf0 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3783,6 +3783,11 @@ static inline bool isar_feature_aa32_predinv(const
ARMISARegisters *id)
return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
}
+static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id)
+{
+ return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0;
+}
+
static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
{
return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index 2d94369750d..5befaec87b1 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -50,6 +50,8 @@ VSDOT 1111 110 00 . 10 .... .... 1101 . q:1 . 0 ....
\
vm=%vm_dp vn=%vn_dp vd=%vd_dp
VUDOT 1111 110 00 . 10 .... .... 1101 . q:1 . 1 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VUSDOT 1111 110 01 . 10 .... .... 1101 . q:1 . 0 .... \
+ vm=%vm_dp vn=%vn_dp vd=%vd_dp
# VFM[AS]L
VFML 1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \
@@ -66,6 +68,10 @@ VSDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1
0 vm:4 \
vn=%vn_dp vd=%vd_dp
VUDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 1 vm:4 \
vn=%vn_dp vd=%vd_dp
+VUSDOT_scalar 1111 1110 1 . 00 .... .... 1101 . q:1 index:1 0 vm:4 \
+ vn=%vn_dp vd=%vd_dp
+VSUDOT_scalar 1111 1110 1 . 00 .... .... 1101 . q:1 index:1 1 vm:4 \
+ vn=%vn_dp vd=%vd_dp
%vfml_scalar_q0_rm 0:3 5:1
%vfml_scalar_q1_index 5:1 3:1
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index 386b42fe4b0..b6ca29c25ca 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -287,6 +287,15 @@ static bool trans_VUDOT(DisasContext *s, arg_VUDOT *a)
gen_helper_gvec_udot_b);
}
+static bool trans_VUSDOT(DisasContext *s, arg_VUSDOT *a)
+{
+ if (!dc_isar_feature(aa32_i8mm, s)) {
+ return false;
+ }
+ return do_neon_ddda(s, a->q * 7, a->vd, a->vn, a->vm, 0,
+ gen_helper_gvec_usdot_b);
+}
+
static bool trans_VFML(DisasContext *s, arg_VFML *a)
{
int opr_sz;
@@ -354,6 +363,24 @@ static bool trans_VUDOT_scalar(DisasContext *s,
arg_VUDOT_scalar *a)
gen_helper_gvec_udot_idx_b);
}
+static bool trans_VUSDOT_scalar(DisasContext *s, arg_VUSDOT_scalar *a)
+{
+ if (!dc_isar_feature(aa32_i8mm, s)) {
+ return false;
+ }
+ return do_neon_ddda(s, a->q * 6, a->vd, a->vn, a->vm, a->index,
+ gen_helper_gvec_usdot_idx_b);
+}
+
+static bool trans_VSUDOT_scalar(DisasContext *s, arg_VSUDOT_scalar *a)
+{
+ if (!dc_isar_feature(aa32_i8mm, s)) {
+ return false;
+ }
+ return do_neon_ddda(s, a->q * 6, a->vd, a->vn, a->vm, a->index,
+ gen_helper_gvec_sudot_idx_b);
+}
+
static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
{
int opr_sz;
--
2.20.1
- [PULL 101/114] target/arm: Implement 128-bit ZIP, UZP, TRN, (continued)
- [PULL 101/114] target/arm: Implement 128-bit ZIP, UZP, TRN, Peter Maydell, 2021/05/25
- [PULL 104/114] target/arm: Implement SVE2 fp multiply-add long, Peter Maydell, 2021/05/25
- [PULL 105/114] target/arm: Implement aarch64 SUDOT, USDOT, Peter Maydell, 2021/05/25
- [PULL 110/114] target/arm: Split decode of VSDOT and VUDOT, Peter Maydell, 2021/05/25
- [PULL 114/114] target/arm: Enable SVE2 and related extensions, Peter Maydell, 2021/05/25
- [PULL 107/114] target/arm: Remove unused fpst from VDOT_scalar, Peter Maydell, 2021/05/25
- [PULL 112/114] target/arm: Implement integer matrix multiply accumulate, Peter Maydell, 2021/05/25
- [PULL 113/114] linux-user/aarch64: Enable hwcap bits for sve2 and related extensions, Peter Maydell, 2021/05/25
- [PULL 098/114] target/arm: Share table of sve load functions, Peter Maydell, 2021/05/25
- [PULL 097/114] target/arm: Implement SVE2 FLOGB, Peter Maydell, 2021/05/25
- [PULL 111/114] target/arm: Implement aarch32 VSUDOT, VUSDOT,
Peter Maydell <=