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[PULL 105/114] target/arm: Implement aarch64 SUDOT, USDOT
From: |
Peter Maydell |
Subject: |
[PULL 105/114] target/arm: Implement aarch64 SUDOT, USDOT |
Date: |
Tue, 25 May 2021 16:07:27 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-84-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 5 +++++
target/arm/translate-a64.c | 25 +++++++++++++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 55383cb0661..8ecb2a1c89e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -4216,6 +4216,11 @@ static inline bool isar_feature_aa64_rcpc_8_4(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
}
+static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
+}
+
static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index a8edd2d2815..c8754817842 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -12175,6 +12175,13 @@ static void
disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
}
feature = dc_isar_feature(aa64_dp, s);
break;
+ case 0x03: /* USDOT */
+ if (size != MO_32) {
+ unallocated_encoding(s);
+ return;
+ }
+ feature = dc_isar_feature(aa64_i8mm, s);
+ break;
case 0x18: /* FCMLA, #0 */
case 0x19: /* FCMLA, #90 */
case 0x1a: /* FCMLA, #180 */
@@ -12215,6 +12222,10 @@ static void
disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b);
return;
+ case 0x3: /* USDOT */
+ gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, 0, gen_helper_gvec_usdot_b);
+ return;
+
case 0x8: /* FCMLA, #0 */
case 0x9: /* FCMLA, #90 */
case 0xa: /* FCMLA, #180 */
@@ -13360,6 +13371,13 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
return;
}
break;
+ case 0x0f: /* SUDOT, USDOT */
+ if (is_scalar || (size & 1) || !dc_isar_feature(aa64_i8mm, s)) {
+ unallocated_encoding(s);
+ return;
+ }
+ size = MO_32;
+ break;
case 0x11: /* FCMLA #0 */
case 0x13: /* FCMLA #90 */
case 0x15: /* FCMLA #180 */
@@ -13474,6 +13492,13 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
u ? gen_helper_gvec_udot_idx_b
: gen_helper_gvec_sdot_idx_b);
return;
+ case 0x0f: /* SUDOT, USDOT */
+ gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, index,
+ extract32(insn, 23, 1)
+ ? gen_helper_gvec_usdot_idx_b
+ : gen_helper_gvec_sudot_idx_b);
+ return;
+
case 0x11: /* FCMLA #0 */
case 0x13: /* FCMLA #90 */
case 0x15: /* FCMLA #180 */
--
2.20.1
- [PULL 096/114] target/arm: Implement SVE2 FCVTXNT, FCVTX, (continued)
- [PULL 096/114] target/arm: Implement SVE2 FCVTXNT, FCVTX, Peter Maydell, 2021/05/25
- [PULL 099/114] target/arm: Tidy do_ldrq, Peter Maydell, 2021/05/25
- [PULL 100/114] target/arm: Implement SVE2 LD1RO, Peter Maydell, 2021/05/25
- [PULL 103/114] target/arm: Move endian adjustment macros to vec_internal.h, Peter Maydell, 2021/05/25
- [PULL 102/114] target/arm: Implement SVE2 bitwise shift immediate, Peter Maydell, 2021/05/25
- [PULL 106/114] target/arm: Split out do_neon_ddda_fpst, Peter Maydell, 2021/05/25
- [PULL 108/114] target/arm: Fix decode for VDOT (indexed), Peter Maydell, 2021/05/25
- [PULL 109/114] target/arm: Split out do_neon_ddda, Peter Maydell, 2021/05/25
- [PULL 101/114] target/arm: Implement 128-bit ZIP, UZP, TRN, Peter Maydell, 2021/05/25
- [PULL 104/114] target/arm: Implement SVE2 fp multiply-add long, Peter Maydell, 2021/05/25
- [PULL 105/114] target/arm: Implement aarch64 SUDOT, USDOT,
Peter Maydell <=
- [PULL 110/114] target/arm: Split decode of VSDOT and VUDOT, Peter Maydell, 2021/05/25
- [PULL 114/114] target/arm: Enable SVE2 and related extensions, Peter Maydell, 2021/05/25
- [PULL 107/114] target/arm: Remove unused fpst from VDOT_scalar, Peter Maydell, 2021/05/25
- [PULL 112/114] target/arm: Implement integer matrix multiply accumulate, Peter Maydell, 2021/05/25
- [PULL 113/114] linux-user/aarch64: Enable hwcap bits for sve2 and related extensions, Peter Maydell, 2021/05/25
- [PULL 098/114] target/arm: Share table of sve load functions, Peter Maydell, 2021/05/25
- [PULL 097/114] target/arm: Implement SVE2 FLOGB, Peter Maydell, 2021/05/25
- [PULL 111/114] target/arm: Implement aarch32 VSUDOT, VUSDOT, Peter Maydell, 2021/05/25