[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 043/114] target/arm: Implement SVE2 bitwise shift right and accumu
From: |
Peter Maydell |
Subject: |
[PULL 043/114] target/arm: Implement SVE2 bitwise shift right and accumulate |
Date: |
Tue, 25 May 2021 16:02:13 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/sve.decode | 8 ++++++++
target/arm/translate-sve.c | 34 ++++++++++++++++++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 79046d81e3a..d3c4ec6dd12 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1253,3 +1253,11 @@ UABALT 01000101 .. 0 ..... 1100 11 ..... .....
@rda_rn_rm
# ADC and SBC decoded via size in helper dispatch.
ADCLB 01000101 .. 0 ..... 11010 0 ..... ..... @rda_rn_rm
ADCLT 01000101 .. 0 ..... 11010 1 ..... ..... @rda_rn_rm
+
+## SVE2 bitwise shift right and accumulate
+
+# TODO: Use @rda and %reg_movprfx here.
+SSRA 01000101 .. 0 ..... 1110 00 ..... ..... @rd_rn_tszimm_shr
+USRA 01000101 .. 0 ..... 1110 01 ..... ..... @rd_rn_tszimm_shr
+SRSRA 01000101 .. 0 ..... 1110 10 ..... ..... @rd_rn_tszimm_shr
+URSRA 01000101 .. 0 ..... 1110 11 ..... ..... @rd_rn_tszimm_shr
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index cf4fa50ad2a..1f93b1e3fe3 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -6394,3 +6394,37 @@ static bool trans_ADCLT(DisasContext *s, arg_rrrr_esz *a)
{
return do_adcl(s, a, true);
}
+
+static bool do_sve2_fn2i(DisasContext *s, arg_rri_esz *a, GVecGen2iFn *fn)
+{
+ if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ unsigned rd_ofs = vec_full_reg_offset(s, a->rd);
+ unsigned rn_ofs = vec_full_reg_offset(s, a->rn);
+ fn(a->esz, rd_ofs, rn_ofs, a->imm, vsz, vsz);
+ }
+ return true;
+}
+
+static bool trans_SSRA(DisasContext *s, arg_rri_esz *a)
+{
+ return do_sve2_fn2i(s, a, gen_gvec_ssra);
+}
+
+static bool trans_USRA(DisasContext *s, arg_rri_esz *a)
+{
+ return do_sve2_fn2i(s, a, gen_gvec_usra);
+}
+
+static bool trans_SRSRA(DisasContext *s, arg_rri_esz *a)
+{
+ return do_sve2_fn2i(s, a, gen_gvec_srsra);
+}
+
+static bool trans_URSRA(DisasContext *s, arg_rri_esz *a)
+{
+ return do_sve2_fn2i(s, a, gen_gvec_ursra);
+}
--
2.20.1
- [PULL 049/114] target/arm: Implement SVE2 SQSHRUN, SQRSHRUN, (continued)
- [PULL 049/114] target/arm: Implement SVE2 SQSHRUN, SQRSHRUN, Peter Maydell, 2021/05/25
- [PULL 046/114] target/arm: Implement SVE2 saturating extract narrow, Peter Maydell, 2021/05/25
- [PULL 050/114] target/arm: Implement SVE2 UQSHRN, UQRSHRN, Peter Maydell, 2021/05/25
- [PULL 053/114] target/arm: Implement SVE2 WHILERW, WHILEWR, Peter Maydell, 2021/05/25
- [PULL 052/114] target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS, Peter Maydell, 2021/05/25
- [PULL 055/114] target/arm: Implement SVE2 MATCH, NMATCH, Peter Maydell, 2021/05/25
- [PULL 042/114] target/arm: Implement SVE2 integer add/subtract long with carry, Peter Maydell, 2021/05/25
- [PULL 057/114] target/arm: Implement SVE2 saturating multiply-add high, Peter Maydell, 2021/05/25
- [PULL 061/114] target/arm: Implement SVE2 RADDHNB, RADDHNT, Peter Maydell, 2021/05/25
- [PULL 044/114] target/arm: Implement SVE2 bitwise shift and insert, Peter Maydell, 2021/05/25
- [PULL 043/114] target/arm: Implement SVE2 bitwise shift right and accumulate,
Peter Maydell <=
- [PULL 035/114] target/arm: Implement SVE2 integer multiply long, Peter Maydell, 2021/05/25
- [PULL 048/114] target/arm: Implement SVE2 SHRN, RSHRN, Peter Maydell, 2021/05/25
- [PULL 045/114] target/arm: Implement SVE2 integer absolute difference and accumulate, Peter Maydell, 2021/05/25
- [PULL 051/114] target/arm: Implement SVE2 SQSHRN, SQRSHRN, Peter Maydell, 2021/05/25
- [PULL 056/114] target/arm: Implement SVE2 saturating multiply-add long, Peter Maydell, 2021/05/25
- [PULL 054/114] target/arm: Implement SVE2 bitwise ternary operations, Peter Maydell, 2021/05/25
- [PULL 058/114] target/arm: Implement SVE2 integer multiply-add long, Peter Maydell, 2021/05/25
- [PULL 060/114] target/arm: Implement SVE2 ADDHNB, ADDHNT, Peter Maydell, 2021/05/25
- [PULL 063/114] target/arm: Implement SVE2 RSUBHNB, RSUBHNT, Peter Maydell, 2021/05/25
- [PULL 059/114] target/arm: Implement SVE2 complex integer multiply-add, Peter Maydell, 2021/05/25