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[PULL 012/114] accel/tlb: Rename TLBFlushPageBitsByMMUIdxData -> TLBFlus
From: |
Peter Maydell |
Subject: |
[PULL 012/114] accel/tlb: Rename TLBFlushPageBitsByMMUIdxData -> TLBFlushRangeData |
Date: |
Tue, 25 May 2021 16:01:42 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Rename the structure to match the rename of tlb_flush_range_locked.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210509151618.2331764-4-f4bug@amsat.org
Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
accel/tcg/cputlb.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index df5d5dbf879..36e7831ef70 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -762,11 +762,11 @@ typedef struct {
target_ulong len;
uint16_t idxmap;
uint16_t bits;
-} TLBFlushPageBitsByMMUIdxData;
+} TLBFlushRangeData;
static void
tlb_flush_page_bits_by_mmuidx_async_0(CPUState *cpu,
- TLBFlushPageBitsByMMUIdxData d)
+ TLBFlushRangeData d)
{
CPUArchState *env = cpu->env_ptr;
int mmu_idx;
@@ -790,7 +790,7 @@ tlb_flush_page_bits_by_mmuidx_async_0(CPUState *cpu,
}
static bool encode_pbm_to_runon(run_on_cpu_data *out,
- TLBFlushPageBitsByMMUIdxData d)
+ TLBFlushRangeData d)
{
/* We need 6 bits to hold to hold @bits up to 63. */
if (d.idxmap <= MAKE_64BIT_MASK(0, TARGET_PAGE_BITS - 6)) {
@@ -800,11 +800,11 @@ static bool encode_pbm_to_runon(run_on_cpu_data *out,
return false;
}
-static TLBFlushPageBitsByMMUIdxData
+static TLBFlushRangeData
decode_runon_to_pbm(run_on_cpu_data data)
{
target_ulong addr_map_bits = (target_ulong) data.target_ptr;
- return (TLBFlushPageBitsByMMUIdxData){
+ return (TLBFlushRangeData){
.addr = addr_map_bits & TARGET_PAGE_MASK,
.idxmap = (addr_map_bits & ~TARGET_PAGE_MASK) >> 6,
.bits = addr_map_bits & 0x3f
@@ -820,7 +820,7 @@ static void tlb_flush_page_bits_by_mmuidx_async_1(CPUState
*cpu,
static void tlb_flush_page_bits_by_mmuidx_async_2(CPUState *cpu,
run_on_cpu_data data)
{
- TLBFlushPageBitsByMMUIdxData *d = data.host_ptr;
+ TLBFlushRangeData *d = data.host_ptr;
tlb_flush_page_bits_by_mmuidx_async_0(cpu, *d);
g_free(d);
}
@@ -828,7 +828,7 @@ static void tlb_flush_page_bits_by_mmuidx_async_2(CPUState
*cpu,
void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr,
uint16_t idxmap, unsigned bits)
{
- TLBFlushPageBitsByMMUIdxData d;
+ TLBFlushRangeData d;
run_on_cpu_data runon;
/* If all bits are significant, this devolves to tlb_flush_page. */
@@ -854,7 +854,7 @@ void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
target_ulong addr,
async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_1, runon);
} else {
/* Otherwise allocate a structure, freed by the worker. */
- TLBFlushPageBitsByMMUIdxData *p = g_memdup(&d, sizeof(d));
+ TLBFlushRangeData *p = g_memdup(&d, sizeof(d));
async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_2,
RUN_ON_CPU_HOST_PTR(p));
}
@@ -865,7 +865,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState
*src_cpu,
uint16_t idxmap,
unsigned bits)
{
- TLBFlushPageBitsByMMUIdxData d;
+ TLBFlushRangeData d;
run_on_cpu_data runon;
/* If all bits are significant, this devolves to tlb_flush_page. */
@@ -893,7 +893,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState
*src_cpu,
/* Allocate a separate data block for each destination cpu. */
CPU_FOREACH(dst_cpu) {
if (dst_cpu != src_cpu) {
- TLBFlushPageBitsByMMUIdxData *p = g_memdup(&d, sizeof(d));
+ TLBFlushRangeData *p = g_memdup(&d, sizeof(d));
async_run_on_cpu(dst_cpu,
tlb_flush_page_bits_by_mmuidx_async_2,
RUN_ON_CPU_HOST_PTR(p));
@@ -909,7 +909,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState
*src_cpu,
uint16_t idxmap,
unsigned bits)
{
- TLBFlushPageBitsByMMUIdxData d;
+ TLBFlushRangeData d;
run_on_cpu_data runon;
/* If all bits are significant, this devolves to tlb_flush_page. */
@@ -935,7 +935,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState
*src_cpu,
runon);
} else {
CPUState *dst_cpu;
- TLBFlushPageBitsByMMUIdxData *p;
+ TLBFlushRangeData *p;
/* Allocate a separate data block for each destination cpu. */
CPU_FOREACH(dst_cpu) {
--
2.20.1
- [PULL 002/114] hw/intc/arm_gicv3_cpuif: Fix EOIR write access check logic, (continued)
- [PULL 002/114] hw/intc/arm_gicv3_cpuif: Fix EOIR write access check logic, Peter Maydell, 2021/05/25
- [PULL 004/114] hw/arm/mps2-tz: Make SRAM_ADDR_WIDTH board-specific, Peter Maydell, 2021/05/25
- [PULL 009/114] target/arm: Use correct SP in M-profile exception return, Peter Maydell, 2021/05/25
- [PULL 008/114] hw/arm: Model TCMs in the SSE-300, not the AN547, Peter Maydell, 2021/05/25
- [PULL 005/114] hw/arm/armsse.c: Correct modelling of SSE-300 internal SRAMs, Peter Maydell, 2021/05/25
- [PULL 007/114] hw/arm/mps2-tz: Allow board to specify a boot RAM size, Peter Maydell, 2021/05/25
- [PULL 011/114] accel/tcg: Pass length argument to tlb_flush_range_locked(), Peter Maydell, 2021/05/25
- [PULL 010/114] accel/tcg: Replace g_new() + memcpy() by g_memdup(), Peter Maydell, 2021/05/25
- [PULL 006/114] hw/arm/armsse: Convert armsse_realize() to use ERRP_GUARD, Peter Maydell, 2021/05/25
- [PULL 017/114] accel/tcg: Rename tlb_flush_page_bits -> range]_by_mmuidx_async_0, Peter Maydell, 2021/05/25
- [PULL 012/114] accel/tlb: Rename TLBFlushPageBitsByMMUIdxData -> TLBFlushRangeData,
Peter Maydell <=
- [PULL 013/114] accel/tcg: Remove {encode,decode}_pbm_to_runon, Peter Maydell, 2021/05/25
- [PULL 016/114] accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced(), Peter Maydell, 2021/05/25
- [PULL 018/114] accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_async_[2 > 1], Peter Maydell, 2021/05/25
- [PULL 014/114] accel/tcg: Add tlb_flush_range_by_mmuidx(), Peter Maydell, 2021/05/25
- [PULL 015/114] accel/tcg: Add tlb_flush_range_by_mmuidx_all_cpus(), Peter Maydell, 2021/05/25
- [PULL 020/114] target/arm: Add support for FEAT_TLBIOS, Peter Maydell, 2021/05/25
- [PULL 021/114] target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type, Peter Maydell, 2021/05/25
- [PULL 019/114] target/arm: Add support for FEAT_TLBIRANGE, Peter Maydell, 2021/05/25
- [PULL 023/114] target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2, Peter Maydell, 2021/05/25
- [PULL 024/114] target/arm: Implement SVE2 Integer Multiply - Unpredicated, Peter Maydell, 2021/05/25