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[PULL 010/114] accel/tcg: Replace g_new() + memcpy() by g_memdup()
From: |
Peter Maydell |
Subject: |
[PULL 010/114] accel/tcg: Replace g_new() + memcpy() by g_memdup() |
Date: |
Tue, 25 May 2021 16:01:40 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Using g_memdup is a bit more compact than g_new + memcpy.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210509151618.2331764-2-f4bug@amsat.org
Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
accel/tcg/cputlb.c | 15 ++++-----------
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 84e7d91a5ca..f616b58a898 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -837,11 +837,8 @@ void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
target_ulong addr,
} else if (encode_pbm_to_runon(&runon, d)) {
async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_1, runon);
} else {
- TLBFlushPageBitsByMMUIdxData *p
- = g_new(TLBFlushPageBitsByMMUIdxData, 1);
-
/* Otherwise allocate a structure, freed by the worker. */
- *p = d;
+ TLBFlushPageBitsByMMUIdxData *p = g_memdup(&d, sizeof(d));
async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_2,
RUN_ON_CPU_HOST_PTR(p));
}
@@ -875,13 +872,11 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState
*src_cpu,
flush_all_helper(src_cpu, tlb_flush_page_bits_by_mmuidx_async_1,
runon);
} else {
CPUState *dst_cpu;
- TLBFlushPageBitsByMMUIdxData *p;
/* Allocate a separate data block for each destination cpu. */
CPU_FOREACH(dst_cpu) {
if (dst_cpu != src_cpu) {
- p = g_new(TLBFlushPageBitsByMMUIdxData, 1);
- *p = d;
+ TLBFlushPageBitsByMMUIdxData *p = g_memdup(&d, sizeof(d));
async_run_on_cpu(dst_cpu,
tlb_flush_page_bits_by_mmuidx_async_2,
RUN_ON_CPU_HOST_PTR(p));
@@ -927,15 +922,13 @@ void
tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
/* Allocate a separate data block for each destination cpu. */
CPU_FOREACH(dst_cpu) {
if (dst_cpu != src_cpu) {
- p = g_new(TLBFlushPageBitsByMMUIdxData, 1);
- *p = d;
+ p = g_memdup(&d, sizeof(d));
async_run_on_cpu(dst_cpu,
tlb_flush_page_bits_by_mmuidx_async_2,
RUN_ON_CPU_HOST_PTR(p));
}
}
- p = g_new(TLBFlushPageBitsByMMUIdxData, 1);
- *p = d;
+ p = g_memdup(&d, sizeof(d));
async_safe_run_on_cpu(src_cpu, tlb_flush_page_bits_by_mmuidx_async_2,
RUN_ON_CPU_HOST_PTR(p));
}
--
2.20.1
- [PULL 000/114] target-arm queue, Peter Maydell, 2021/05/25
- [PULL 001/114] hw/arm/smmuv3: Another range invalidation fix, Peter Maydell, 2021/05/25
- [PULL 003/114] hw/arm/mps2-tz: Don't duplicate modelling of SRAM in AN524, Peter Maydell, 2021/05/25
- [PULL 002/114] hw/intc/arm_gicv3_cpuif: Fix EOIR write access check logic, Peter Maydell, 2021/05/25
- [PULL 004/114] hw/arm/mps2-tz: Make SRAM_ADDR_WIDTH board-specific, Peter Maydell, 2021/05/25
- [PULL 009/114] target/arm: Use correct SP in M-profile exception return, Peter Maydell, 2021/05/25
- [PULL 008/114] hw/arm: Model TCMs in the SSE-300, not the AN547, Peter Maydell, 2021/05/25
- [PULL 005/114] hw/arm/armsse.c: Correct modelling of SSE-300 internal SRAMs, Peter Maydell, 2021/05/25
- [PULL 007/114] hw/arm/mps2-tz: Allow board to specify a boot RAM size, Peter Maydell, 2021/05/25
- [PULL 011/114] accel/tcg: Pass length argument to tlb_flush_range_locked(), Peter Maydell, 2021/05/25
- [PULL 010/114] accel/tcg: Replace g_new() + memcpy() by g_memdup(),
Peter Maydell <=
- [PULL 006/114] hw/arm/armsse: Convert armsse_realize() to use ERRP_GUARD, Peter Maydell, 2021/05/25
- [PULL 017/114] accel/tcg: Rename tlb_flush_page_bits -> range]_by_mmuidx_async_0, Peter Maydell, 2021/05/25
- [PULL 012/114] accel/tlb: Rename TLBFlushPageBitsByMMUIdxData -> TLBFlushRangeData, Peter Maydell, 2021/05/25
- [PULL 013/114] accel/tcg: Remove {encode,decode}_pbm_to_runon, Peter Maydell, 2021/05/25
- [PULL 016/114] accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced(), Peter Maydell, 2021/05/25
- [PULL 018/114] accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_async_[2 > 1], Peter Maydell, 2021/05/25
- [PULL 014/114] accel/tcg: Add tlb_flush_range_by_mmuidx(), Peter Maydell, 2021/05/25
- [PULL 015/114] accel/tcg: Add tlb_flush_range_by_mmuidx_all_cpus(), Peter Maydell, 2021/05/25
- [PULL 020/114] target/arm: Add support for FEAT_TLBIOS, Peter Maydell, 2021/05/25
- [PULL 021/114] target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type, Peter Maydell, 2021/05/25