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[PATCH v7 64/92] target/arm: Macroize helper_gvec_{s,u}dot_{b,h}
From: |
Richard Henderson |
Subject: |
[PATCH v7 64/92] target/arm: Macroize helper_gvec_{s,u}dot_{b,h} |
Date: |
Mon, 24 May 2021 18:03:30 -0700 |
We're about to add more variations on this theme.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/vec_helper.c | 82 ++++++++++-------------------------------
1 file changed, 20 insertions(+), 62 deletions(-)
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index 8b7269d8e1..cddf095c74 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -543,73 +543,31 @@ void HELPER(sve2_sqrdmulh_idx_d)(void *vd, void *vn, void
*vm, uint32_t desc)
/* Integer 8 and 16-bit dot-product.
*
* Note that for the loops herein, host endianness does not matter
- * with respect to the ordering of data within the 64-bit lanes.
+ * with respect to the ordering of data within the quad-width lanes.
* All elements are treated equally, no matter where they are.
*/
-void HELPER(gvec_sdot_b)(void *vd, void *vn, void *vm, void *va, uint32_t desc)
-{
- intptr_t i, opr_sz = simd_oprsz(desc);
- int32_t *d = vd, *a = va;
- int8_t *n = vn, *m = vm;
-
- for (i = 0; i < opr_sz / 4; ++i) {
- d[i] = (a[i] +
- n[i * 4 + 0] * m[i * 4 + 0] +
- n[i * 4 + 1] * m[i * 4 + 1] +
- n[i * 4 + 2] * m[i * 4 + 2] +
- n[i * 4 + 3] * m[i * 4 + 3]);
- }
- clear_tail(d, opr_sz, simd_maxsz(desc));
+#define DO_DOT(NAME, TYPED, TYPEN, TYPEM) \
+void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, uint32_t desc) \
+{ \
+ intptr_t i, opr_sz = simd_oprsz(desc); \
+ TYPED *d = vd, *a = va; \
+ TYPEN *n = vn; \
+ TYPEM *m = vm; \
+ for (i = 0; i < opr_sz / sizeof(TYPED); ++i) { \
+ d[i] = (a[i] + \
+ (TYPED)n[i * 4 + 0] * m[i * 4 + 0] + \
+ (TYPED)n[i * 4 + 1] * m[i * 4 + 1] + \
+ (TYPED)n[i * 4 + 2] * m[i * 4 + 2] + \
+ (TYPED)n[i * 4 + 3] * m[i * 4 + 3]); \
+ } \
+ clear_tail(d, opr_sz, simd_maxsz(desc)); \
}
-void HELPER(gvec_udot_b)(void *vd, void *vn, void *vm, void *va, uint32_t desc)
-{
- intptr_t i, opr_sz = simd_oprsz(desc);
- uint32_t *d = vd, *a = va;
- uint8_t *n = vn, *m = vm;
-
- for (i = 0; i < opr_sz / 4; ++i) {
- d[i] = (a[i] +
- n[i * 4 + 0] * m[i * 4 + 0] +
- n[i * 4 + 1] * m[i * 4 + 1] +
- n[i * 4 + 2] * m[i * 4 + 2] +
- n[i * 4 + 3] * m[i * 4 + 3]);
- }
- clear_tail(d, opr_sz, simd_maxsz(desc));
-}
-
-void HELPER(gvec_sdot_h)(void *vd, void *vn, void *vm, void *va, uint32_t desc)
-{
- intptr_t i, opr_sz = simd_oprsz(desc);
- int64_t *d = vd, *a = va;
- int16_t *n = vn, *m = vm;
-
- for (i = 0; i < opr_sz / 8; ++i) {
- d[i] = (a[i] +
- (int64_t)n[i * 4 + 0] * m[i * 4 + 0] +
- (int64_t)n[i * 4 + 1] * m[i * 4 + 1] +
- (int64_t)n[i * 4 + 2] * m[i * 4 + 2] +
- (int64_t)n[i * 4 + 3] * m[i * 4 + 3]);
- }
- clear_tail(d, opr_sz, simd_maxsz(desc));
-}
-
-void HELPER(gvec_udot_h)(void *vd, void *vn, void *vm, void *va, uint32_t desc)
-{
- intptr_t i, opr_sz = simd_oprsz(desc);
- uint64_t *d = vd, *a = va;
- uint16_t *n = vn, *m = vm;
-
- for (i = 0; i < opr_sz / 8; ++i) {
- d[i] = (a[i] +
- (uint64_t)n[i * 4 + 0] * m[i * 4 + 0] +
- (uint64_t)n[i * 4 + 1] * m[i * 4 + 1] +
- (uint64_t)n[i * 4 + 2] * m[i * 4 + 2] +
- (uint64_t)n[i * 4 + 3] * m[i * 4 + 3]);
- }
- clear_tail(d, opr_sz, simd_maxsz(desc));
-}
+DO_DOT(gvec_sdot_b, int32_t, int8_t, int8_t)
+DO_DOT(gvec_udot_b, uint32_t, uint8_t, uint8_t)
+DO_DOT(gvec_sdot_h, int64_t, int16_t, int16_t)
+DO_DOT(gvec_udot_h, uint64_t, uint16_t, uint16_t)
void HELPER(gvec_sdot_idx_b)(void *vd, void *vn, void *vm,
void *va, uint32_t desc)
--
2.25.1
- [PATCH v7 30/92] target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS, (continued)
- [PATCH v7 30/92] target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS, Richard Henderson, 2021/05/24
- [PATCH v7 37/92] target/arm: Implement SVE2 complex integer multiply-add, Richard Henderson, 2021/05/24
- [PATCH v7 31/92] target/arm: Implement SVE2 WHILERW, WHILEWR, Richard Henderson, 2021/05/24
- [PATCH v7 33/92] target/arm: Implement SVE2 MATCH, NMATCH, Richard Henderson, 2021/05/24
- [PATCH v7 39/92] target/arm: Implement SVE2 RADDHNB, RADDHNT, Richard Henderson, 2021/05/24
- [PATCH v7 40/92] target/arm: Implement SVE2 SUBHNB, SUBHNT, Richard Henderson, 2021/05/24
- [PATCH v7 41/92] target/arm: Implement SVE2 RSUBHNB, RSUBHNT, Richard Henderson, 2021/05/24
- [PATCH v7 42/92] target/arm: Implement SVE2 HISTCNT, HISTSEG, Richard Henderson, 2021/05/24
- [PATCH v7 43/92] target/arm: Implement SVE2 XAR, Richard Henderson, 2021/05/24
- [PATCH v7 44/92] target/arm: Implement SVE2 scatter store insns, Richard Henderson, 2021/05/24
- [PATCH v7 64/92] target/arm: Macroize helper_gvec_{s,u}dot_{b,h},
Richard Henderson <=
- [PATCH v7 48/92] target/arm: Use correct output type for gvec_sdot_*_b, Richard Henderson, 2021/05/24
- [PATCH v7 49/92] target/arm: Pass separate addend to {U, S}DOT helpers, Richard Henderson, 2021/05/24
- [PATCH v7 56/92] target/arm: Implement SVE2 saturating multiply-add (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 55/92] target/arm: Implement SVE2 saturating multiply-add high (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 59/92] target/arm: Implement SVE2 saturating multiply high (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 47/92] target/arm: Implement SVE2 SPLICE, EXT, Richard Henderson, 2021/05/24
- [PATCH v7 60/92] target/arm: Implement SVE2 multiply-add long (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 68/92] target/arm: Implement SVE2 crypto unary operations, Richard Henderson, 2021/05/24
- [PATCH v7 52/92] target/arm: Split out formats for 3 vectors + 1 index, Richard Henderson, 2021/05/24
- [PATCH v7 45/92] target/arm: Implement SVE2 gather load insns, Richard Henderson, 2021/05/24