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[PATCH v7 41/92] target/arm: Implement SVE2 RSUBHNB, RSUBHNT
From: |
Richard Henderson |
Subject: |
[PATCH v7 41/92] target/arm: Implement SVE2 RSUBHNB, RSUBHNT |
Date: |
Mon, 24 May 2021 18:03:07 -0700 |
From: Stephen Long <steplong@quicinc.com>
This completes the section 'SVE2 integer add/subtract narrow high part'
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Message-Id: <20200417162231.10374-5-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Fix round bit type (laurent desnogues)
---
target/arm/helper-sve.h | 8 ++++++++
target/arm/sve.decode | 2 ++
target/arm/sve_helper.c | 10 ++++++++++
target/arm/translate-sve.c | 2 ++
4 files changed, 22 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 3642e7c820..98e6b57e38 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2533,6 +2533,14 @@ DEF_HELPER_FLAGS_4(sve2_subhnt_h, TCG_CALL_NO_RWG, void,
ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_subhnt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_subhnt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_rsubhnb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_rsubhnb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_rsubhnb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(sve2_rsubhnt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_rsubhnt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_rsubhnt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_5(sve2_match_ppzz_b, TCG_CALL_NO_RWG,
i32, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_match_ppzz_h, TCG_CALL_NO_RWG,
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index c68bfcf6ed..388bf92acf 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1328,6 +1328,8 @@ RADDHNB 01000101 .. 1 ..... 011 010 ..... .....
@rd_rn_rm
RADDHNT 01000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm
SUBHNB 01000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm
SUBHNT 01000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm
+RSUBHNB 01000101 .. 1 ..... 011 110 ..... ..... @rd_rn_rm
+RSUBHNT 01000101 .. 1 ..... 011 111 ..... ..... @rd_rn_rm
### SVE2 Character Match
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 922df9575a..891f6ff453 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -2146,6 +2146,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t
desc) \
#define DO_ADDHN(N, M, SH) ((N + M) >> SH)
#define DO_RADDHN(N, M, SH) ((N + M + ((__typeof(N))1 << (SH - 1))) >> SH)
#define DO_SUBHN(N, M, SH) ((N - M) >> SH)
+#define DO_RSUBHN(N, M, SH) ((N - M + ((__typeof(N))1 << (SH - 1))) >> SH)
DO_BINOPNB(sve2_addhnb_h, uint16_t, uint8_t, 8, DO_ADDHN)
DO_BINOPNB(sve2_addhnb_s, uint32_t, uint16_t, 16, DO_ADDHN)
@@ -2171,6 +2172,15 @@ DO_BINOPNT(sve2_subhnt_h, uint16_t, uint8_t, 8, H1_2,
H1, DO_SUBHN)
DO_BINOPNT(sve2_subhnt_s, uint32_t, uint16_t, 16, H1_4, H1_2, DO_SUBHN)
DO_BINOPNT(sve2_subhnt_d, uint64_t, uint32_t, 32, , H1_4, DO_SUBHN)
+DO_BINOPNB(sve2_rsubhnb_h, uint16_t, uint8_t, 8, DO_RSUBHN)
+DO_BINOPNB(sve2_rsubhnb_s, uint32_t, uint16_t, 16, DO_RSUBHN)
+DO_BINOPNB(sve2_rsubhnb_d, uint64_t, uint32_t, 32, DO_RSUBHN)
+
+DO_BINOPNT(sve2_rsubhnt_h, uint16_t, uint8_t, 8, H1_2, H1, DO_RSUBHN)
+DO_BINOPNT(sve2_rsubhnt_s, uint32_t, uint16_t, 16, H1_4, H1_2, DO_RSUBHN)
+DO_BINOPNT(sve2_rsubhnt_d, uint64_t, uint32_t, 32, , H1_4, DO_RSUBHN)
+
+#undef DO_RSUBHN
#undef DO_SUBHN
#undef DO_RADDHN
#undef DO_ADDHN
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 334c57b44f..484d4218b5 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7479,6 +7479,8 @@ DO_SVE2_ZZZ_NARROW(RADDHNT, raddhnt)
DO_SVE2_ZZZ_NARROW(SUBHNB, subhnb)
DO_SVE2_ZZZ_NARROW(SUBHNT, subhnt)
+DO_SVE2_ZZZ_NARROW(RSUBHNB, rsubhnb)
+DO_SVE2_ZZZ_NARROW(RSUBHNT, rsubhnt)
static bool do_sve2_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
gen_helper_gvec_flags_4 *fn)
--
2.25.1
- [PATCH v7 38/92] target/arm: Implement SVE2 ADDHNB, ADDHNT, (continued)
- [PATCH v7 38/92] target/arm: Implement SVE2 ADDHNB, ADDHNT, Richard Henderson, 2021/05/24
- [PATCH v7 34/92] target/arm: Implement SVE2 saturating multiply-add long, Richard Henderson, 2021/05/24
- [PATCH v7 36/92] target/arm: Implement SVE2 integer multiply-add long, Richard Henderson, 2021/05/24
- [PATCH v7 35/92] target/arm: Implement SVE2 saturating multiply-add high, Richard Henderson, 2021/05/24
- [PATCH v7 30/92] target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS, Richard Henderson, 2021/05/24
- [PATCH v7 37/92] target/arm: Implement SVE2 complex integer multiply-add, Richard Henderson, 2021/05/24
- [PATCH v7 31/92] target/arm: Implement SVE2 WHILERW, WHILEWR, Richard Henderson, 2021/05/24
- [PATCH v7 33/92] target/arm: Implement SVE2 MATCH, NMATCH, Richard Henderson, 2021/05/24
- [PATCH v7 39/92] target/arm: Implement SVE2 RADDHNB, RADDHNT, Richard Henderson, 2021/05/24
- [PATCH v7 40/92] target/arm: Implement SVE2 SUBHNB, SUBHNT, Richard Henderson, 2021/05/24
- [PATCH v7 41/92] target/arm: Implement SVE2 RSUBHNB, RSUBHNT,
Richard Henderson <=
- [PATCH v7 42/92] target/arm: Implement SVE2 HISTCNT, HISTSEG, Richard Henderson, 2021/05/24
- [PATCH v7 43/92] target/arm: Implement SVE2 XAR, Richard Henderson, 2021/05/24
- [PATCH v7 44/92] target/arm: Implement SVE2 scatter store insns, Richard Henderson, 2021/05/24
- [PATCH v7 64/92] target/arm: Macroize helper_gvec_{s,u}dot_{b,h}, Richard Henderson, 2021/05/24
- [PATCH v7 48/92] target/arm: Use correct output type for gvec_sdot_*_b, Richard Henderson, 2021/05/24
- [PATCH v7 49/92] target/arm: Pass separate addend to {U, S}DOT helpers, Richard Henderson, 2021/05/24
- [PATCH v7 56/92] target/arm: Implement SVE2 saturating multiply-add (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 55/92] target/arm: Implement SVE2 saturating multiply-add high (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 59/92] target/arm: Implement SVE2 saturating multiply high (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 47/92] target/arm: Implement SVE2 SPLICE, EXT, Richard Henderson, 2021/05/24