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[RFC PATCH 5/7] target/i386: Introduce AMD X86XSaveArea sub-union
From: |
David Edmondson |
Subject: |
[RFC PATCH 5/7] target/i386: Introduce AMD X86XSaveArea sub-union |
Date: |
Thu, 20 May 2021 15:56:45 +0100 |
AMD stores the pkru_state at a different offset to Intel.
Signed-off-by: David Edmondson <david.edmondson@oracle.com>
---
target/i386/cpu.h | 17 +++++++++++++++--
target/i386/kvm/kvm.c | 3 ++-
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index f1ce4e3008..99f0d5d851 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1319,7 +1319,8 @@ typedef struct XSavePKRU {
#define XSAVE_OPMASK_OFFSET 0x440
#define XSAVE_ZMM_HI256_OFFSET 0x480
#define XSAVE_HI16_ZMM_OFFSET 0x680
-#define XSAVE_PKRU_OFFSET 0xa80
+#define XSAVE_INTEL_PKRU_OFFSET 0xa80
+#define XSAVE_AMD_PKRU_OFFSET 0x980
typedef struct X86XSaveArea {
X86LegacyXSaveArea legacy;
@@ -1348,6 +1349,16 @@ typedef struct X86XSaveArea {
/* PKRU State: */
XSavePKRU pkru_state;
} intel;
+ struct {
+ /* Ensure that XSavePKRU is properly aligned. */
+ uint8_t padding[XSAVE_AMD_PKRU_OFFSET
+ - sizeof(X86LegacyXSaveArea)
+ - sizeof(X86XSaveHeader)
+ - sizeof(XSaveAVX)];
+
+ /* PKRU State: */
+ XSavePKRU pkru_state;
+ } amd;
};
} X86XSaveArea;
@@ -1370,7 +1381,9 @@ QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea,
intel.hi16_zmm_state)
!= XSAVE_HI16_ZMM_OFFSET);
QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, intel.pkru_state)
- != XSAVE_PKRU_OFFSET);
+ != XSAVE_INTEL_PKRU_OFFSET);
+QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, amd.pkru_state)
+ != XSAVE_AMD_PKRU_OFFSET);
QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
typedef enum TPRAccess {
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 417776a635..9dd7db060d 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -2414,7 +2414,8 @@ ASSERT_OFFSET(XSAVE_BNDCSR_OFFSET, intel.bndcsr_state);
ASSERT_OFFSET(XSAVE_OPMASK_OFFSET, intel.opmask_state);
ASSERT_OFFSET(XSAVE_ZMM_HI256_OFFSET, intel.zmm_hi256_state);
ASSERT_OFFSET(XSAVE_HI16_ZMM_OFFSET, intel.hi16_zmm_state);
-ASSERT_OFFSET(XSAVE_PKRU_OFFSET, intel.pkru_state);
+ASSERT_OFFSET(XSAVE_INTEL_PKRU_OFFSET, intel.pkru_state);
+ASSERT_OFFSET(XSAVE_AMD_PKRU_OFFSET, amd.pkru_state);
static int kvm_put_xsave(X86CPU *cpu)
{
--
2.30.2
- [RFC PATCH 0/7] Support protection keys in an AMD EPYC-Milan VM, David Edmondson, 2021/05/20
- [RFC PATCH 1/7] target/i386: Declare constants for XSAVE offsets, David Edmondson, 2021/05/20
- [RFC PATCH 3/7] target/i386: Clarify the padding requirements of X86XSaveArea, David Edmondson, 2021/05/20
- [RFC PATCH 4/7] target/i386: Prepare for per-vendor X86XSaveArea layout, David Edmondson, 2021/05/20
- [RFC PATCH 5/7] target/i386: Introduce AMD X86XSaveArea sub-union,
David Edmondson <=
- [RFC PATCH 6/7] target/i386: Adjust AMD XSAVE PKRU area offset in CPUID leaf 0xd, David Edmondson, 2021/05/20
- [RFC PATCH 2/7] target/i386: Use constants for XSAVE offsets, David Edmondson, 2021/05/20
- [RFC PATCH 7/7] target/i386: Manipulate only AMD XSAVE state on AMD, David Edmondson, 2021/05/20
- Re: [RFC PATCH 0/7] Support protection keys in an AMD EPYC-Milan VM, no-reply, 2021/05/20