[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC PATCH 3/7] target/i386: Clarify the padding requirements of X86XSav
From: |
David Edmondson |
Subject: |
[RFC PATCH 3/7] target/i386: Clarify the padding requirements of X86XSaveArea |
Date: |
Thu, 20 May 2021 15:56:43 +0100 |
Replace the hard-coded size of offsets or structure elements with
defined constants or sizeof().
Signed-off-by: David Edmondson <david.edmondson@oracle.com>
---
target/i386/cpu.h | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 1fb732f366..0bb365bddf 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1329,7 +1329,13 @@ typedef struct X86XSaveArea {
/* AVX State: */
XSaveAVX avx_state;
- uint8_t padding[960 - 576 - sizeof(XSaveAVX)];
+
+ /* Ensure that XSaveBNDREG is properly aligned. */
+ uint8_t padding[XSAVE_BNDREG_OFFSET
+ - sizeof(X86LegacyXSaveArea)
+ - sizeof(X86XSaveHeader)
+ - sizeof(XSaveAVX)];
+
/* MPX State: */
XSaveBNDREG bndreg_state;
XSaveBNDCSR bndcsr_state;
--
2.30.2
- [RFC PATCH 0/7] Support protection keys in an AMD EPYC-Milan VM, David Edmondson, 2021/05/20
- [RFC PATCH 1/7] target/i386: Declare constants for XSAVE offsets, David Edmondson, 2021/05/20
- [RFC PATCH 3/7] target/i386: Clarify the padding requirements of X86XSaveArea,
David Edmondson <=
- [RFC PATCH 4/7] target/i386: Prepare for per-vendor X86XSaveArea layout, David Edmondson, 2021/05/20
- [RFC PATCH 5/7] target/i386: Introduce AMD X86XSaveArea sub-union, David Edmondson, 2021/05/20
- [RFC PATCH 6/7] target/i386: Adjust AMD XSAVE PKRU area offset in CPUID leaf 0xd, David Edmondson, 2021/05/20
- [RFC PATCH 2/7] target/i386: Use constants for XSAVE offsets, David Edmondson, 2021/05/20
- [RFC PATCH 7/7] target/i386: Manipulate only AMD XSAVE state on AMD, David Edmondson, 2021/05/20
- Re: [RFC PATCH 0/7] Support protection keys in an AMD EPYC-Milan VM, no-reply, 2021/05/20