[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 25/50] target/i386: Leave TF in DisasContext.flags
From: |
Richard Henderson |
Subject: |
[PULL 25/50] target/i386: Leave TF in DisasContext.flags |
Date: |
Wed, 19 May 2021 13:30:25 -0500 |
It's just as easy to clear the flag with AND than assignment.
In two cases the test for the bit can be folded together with
the test for HF_INHIBIT_IRQ_MASK.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20210514151342.384376-26-richard.henderson@linaro.org>
---
target/i386/tcg/translate.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 847502046f..3f6214c624 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -101,7 +101,6 @@ typedef struct DisasContext {
uint8_t vex_v; /* vex vvvv register, without 1's complement. */
CCOp cc_op; /* current CC operation */
bool cc_op_dirty;
- int tf; /* TF cpu flag */
int jmp_opt; /* use direct block chaining for direct jumps */
int repz_opt; /* optimize jumps within repz instructions */
int mem_index; /* select memory access functions */
@@ -2656,7 +2655,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool
recheck_tf, bool jr)
} else if (recheck_tf) {
gen_helper_rechecking_single_step(cpu_env);
tcg_gen_exit_tb(NULL, 0);
- } else if (s->tf) {
+ } else if (s->flags & HF_TF_MASK) {
gen_helper_single_step(cpu_env);
} else if (jr) {
tcg_gen_lookup_and_goto_ptr();
@@ -5540,7 +5539,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
if (s->base.is_jmp) {
gen_jmp_im(s, s->pc - s->cs_base);
if (reg == R_SS) {
- s->tf = 0;
+ s->flags &= ~HF_TF_MASK;
gen_eob_inhibit_irq(s, true);
} else {
gen_eob(s);
@@ -5606,7 +5605,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
if (s->base.is_jmp) {
gen_jmp_im(s, s->pc - s->cs_base);
if (reg == R_SS) {
- s->tf = 0;
+ s->flags &= ~HF_TF_MASK;
gen_eob_inhibit_irq(s, true);
} else {
gen_eob(s);
@@ -8506,7 +8505,6 @@ static void i386_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cpu)
g_assert(LMA(dc) == ((flags & HF_LMA_MASK) != 0));
g_assert(ADDSEG(dc) == ((flags & HF_ADDSEG_MASK) != 0));
- dc->tf = (flags >> TF_SHIFT) & 1;
dc->cc_op = CC_OP_DYNAMIC;
dc->cc_op_dirty = false;
dc->popl_esp_hack = 0;
@@ -8521,8 +8519,8 @@ static void i386_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cpu)
dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX];
dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX];
dc->cpuid_xsave_features = env->features[FEAT_XSAVE];
- dc->jmp_opt = !(dc->tf || dc->base.singlestep_enabled ||
- (flags & HF_INHIBIT_IRQ_MASK));
+ dc->jmp_opt = !(dc->base.singlestep_enabled ||
+ (flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)));
/* Do not optimize repz jumps at all in icount mode, because
rep movsS instructions are execured with different paths
in !repz_opt and repz_opt modes. The first one was used
@@ -8597,7 +8595,7 @@ static void i386_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cpu)
pc_next = disas_insn(dc, cpu);
- if (dc->tf || (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) {
+ if (dc->flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)) {
/* if single step mode, we generate only one instruction and
generate an exception */
/* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
--
2.25.1
- [PULL 29/50] target/i386: Add stub generator for helper_set_dr, (continued)
- [PULL 29/50] target/i386: Add stub generator for helper_set_dr, Richard Henderson, 2021/05/19
- [PULL 19/50] target/i386: Remove DisasContext.f_st as unused, Richard Henderson, 2021/05/19
- [PULL 20/50] target/i386: Reduce DisasContext.flags to uint32_t, Richard Henderson, 2021/05/19
- [PULL 30/50] target/i386: Assert !SVME for user-only, Richard Henderson, 2021/05/19
- [PULL 26/50] target/i386: Reduce DisasContext jmp_opt, repz_opt to bool, Richard Henderson, 2021/05/19
- [PULL 32/50] target/i386: Implement skinit in translate.c, Richard Henderson, 2021/05/19
- [PULL 31/50] target/i386: Assert !GUEST for user-only, Richard Henderson, 2021/05/19
- [PULL 27/50] target/i386: Fix the comment for repz_opt, Richard Henderson, 2021/05/19
- [PULL 28/50] target/i386: Reorder DisasContext members, Richard Henderson, 2021/05/19
- [PULL 36/50] target/i386: Tidy svm_check_intercept from tcg, Richard Henderson, 2021/05/19
- [PULL 25/50] target/i386: Leave TF in DisasContext.flags,
Richard Henderson <=
- [PULL 24/50] target/i386: Reduce DisasContext popl_esp_hack and rip_offset to uint8_t, Richard Henderson, 2021/05/19
- [PULL 39/50] target/i386: Cleanup read_crN, write_crN, lmsw, Richard Henderson, 2021/05/19
- [PULL 34/50] target/i386: Mark some helpers as noreturn, Richard Henderson, 2021/05/19
- [PULL 37/50] target/i386: Remove pc_start argument to gen_svm_check_intercept, Richard Henderson, 2021/05/19
- [PULL 35/50] target/i386: Simplify gen_debug usage, Richard Henderson, 2021/05/19
- [PULL 38/50] target/i386: Remove user stub for cpu_vmexit, Richard Henderson, 2021/05/19
- [PULL 33/50] target/i386: Eliminate SVM helpers for user-only, Richard Henderson, 2021/05/19
- [PULL 40/50] target/i386: Pass env to do_pause and do_hlt, Richard Henderson, 2021/05/19
- [PULL 41/50] target/i386: Move invlpg, hlt, monitor, mwait to sysemu, Richard Henderson, 2021/05/19
- [PULL 42/50] target/i386: Unify invlpg, invlpga, Richard Henderson, 2021/05/19