Re: [PATCH v6 69/82] target/arm: Share table of sve load functions

[Peter Maydell]

On Fri, 30 Apr 2021 at 22:36, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The table used by do_ldrq is a subset of the table used by do_ld_zpa;
> we can share them by passing dtype instead of msz to do_ldrq.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---

> @@ -5512,14 +5514,8 @@ static bool trans_LDNF1_zpri(DisasContext *s, 
> arg_rpri_load *a)
>      return true;
>  }
>
> -static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int msz)
> +static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int 
> dtype)
>  {
> -    static gen_helper_gvec_mem * const fns[2][4] = {
> -        { gen_helper_sve_ld1bb_r,    gen_helper_sve_ld1hh_le_r,
> -          gen_helper_sve_ld1ss_le_r, gen_helper_sve_ld1dd_le_r },
> -        { gen_helper_sve_ld1bb_r,    gen_helper_sve_ld1hh_be_r,
> -          gen_helper_sve_ld1ss_be_r, gen_helper_sve_ld1dd_be_r },
> -    };
>      unsigned vsz = vec_full_reg_size(s);
>      TCGv_ptr t_pg;
>      TCGv_i32 t_desc;
> @@ -5551,7 +5547,9 @@ static void do_ldrq(DisasContext *s, int zt, int pg, 
> TCGv_i64 addr, int msz)
>      t_pg = tcg_temp_new_ptr();
>      tcg_gen_addi_ptr(t_pg, cpu_env, poff);
>
> -    fns[s->be_data == MO_BE][msz](cpu_env, t_pg, addr, t_desc);
> +    gen_helper_gvec_mem *fn
> +        = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
> +    fn(cpu_env, t_pg, addr, t_desc);

Previously we didn't take account of MTE state, and now we do.
Is this an intentional behaviour change?

If it's fixing a bug, the commit message should say so.

thanks
-- PMM