GICv3 for MTTCG

[Andrey Shinkevich]

Dear colleagues,

I am looking for ways to accelerate the MTTCG for ARM guest on x86-64 host.
The maximum number of CPUs for MTTCG that uses GICv2 is limited by 8:

include/hw/intc/arm_gic_common.h:#define GIC_NCPU 8

The version 3 of the Generic Interrupt Controller (GICv3) is not
supported in QEMU for some reason unknown to me. It would allow to
increase the limit of CPUs and accelerate the MTTCG performance on a
multiple core hypervisor.
I have got an idea to implement the Interrupt Translation Service (ITS)
for using by MTTCG for ARM architecture.

Do you find that idea useful and feasible?
If yes, how much time do you estimate for such a project to complete by
one developer?
If no, what are reasons for not implementing GICv3 for MTTCG in QEMU?

Best regards,
Andrey Shinkevich