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[PULL 23/33] target/i386: move paging mode constants from SVM to cpu.h
From: |
Paolo Bonzini |
Subject: |
[PULL 23/33] target/i386: move paging mode constants from SVM to cpu.h |
Date: |
Tue, 11 May 2021 04:13:40 -0400 |
We will reuse the page walker for both SVM and regular accesses. To do
so we will build a function that receives the currently active paging
mode; start by including in cpu.h the constants and the function to go
from cr4/hflags/efer to the paging mode.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.h | 8 ++++++++
target/i386/svm.h | 5 -----
target/i386/tcg/sysemu/excp_helper.c | 26 ++++++++++++++++++++++----
target/i386/tcg/sysemu/svm_helper.c | 13 +------------
4 files changed, 31 insertions(+), 21 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 0b182b7a5f..dbebd67f98 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -303,6 +303,11 @@ typedef enum X86Seg {
#define PG_ERROR_I_D_MASK 0x10
#define PG_ERROR_PK_MASK 0x20
+#define PG_MODE_PAE (1 << 0)
+#define PG_MODE_LMA (1 << 1)
+#define PG_MODE_NXE (1 << 2)
+#define PG_MODE_PSE (1 << 3)
+
#define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
#define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */
@@ -2105,6 +2110,9 @@ static inline bool cpu_vmx_maybe_enabled(CPUX86State *env)
((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK));
}
+/* excp_helper.c */
+int get_pg_mode(CPUX86State *env);
+
/* fpu_helper.c */
void update_fp_status(CPUX86State *env);
void update_mxcsr_status(CPUX86State *env);
diff --git a/target/i386/svm.h b/target/i386/svm.h
index b515b5ced4..87965e5bc2 100644
--- a/target/i386/svm.h
+++ b/target/i386/svm.h
@@ -132,11 +132,6 @@
#define SVM_NPT_ENABLED (1 << 0)
-#define SVM_NPT_PAE (1 << 0)
-#define SVM_NPT_LMA (1 << 1)
-#define SVM_NPT_NXE (1 << 2)
-#define SVM_NPT_PSE (1 << 3)
-
#define SVM_NPTEXIT_GPA (1ULL << 32)
#define SVM_NPTEXIT_GPT (1ULL << 33)
diff --git a/target/i386/tcg/sysemu/excp_helper.c
b/target/i386/tcg/sysemu/excp_helper.c
index 7697fa4adc..e616ac6f13 100644
--- a/target/i386/tcg/sysemu/excp_helper.c
+++ b/target/i386/tcg/sysemu/excp_helper.c
@@ -21,6 +21,24 @@
#include "cpu.h"
#include "tcg/helper-tcg.h"
+int get_pg_mode(CPUX86State *env)
+{
+ int pg_mode = 0;
+ if (env->cr[4] & CR4_PAE_MASK) {
+ pg_mode |= PG_MODE_PAE;
+ }
+ if (env->cr[4] & CR4_PSE_MASK) {
+ pg_mode |= PG_MODE_PSE;
+ }
+ if (env->hflags & HF_LMA_MASK) {
+ pg_mode |= PG_MODE_LMA;
+ }
+ if (env->efer & MSR_EFER_NXE) {
+ pg_mode |= PG_MODE_NXE;
+ }
+ return pg_mode;
+}
+
static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
int *prot)
{
@@ -37,16 +55,16 @@ static hwaddr get_hphys(CPUState *cs, hwaddr gphys,
MMUAccessType access_type,
return gphys;
}
- if (!(env->nested_pg_mode & SVM_NPT_NXE)) {
+ if (!(env->nested_pg_mode & PG_MODE_NXE)) {
rsvd_mask |= PG_NX_MASK;
}
- if (env->nested_pg_mode & SVM_NPT_PAE) {
+ if (env->nested_pg_mode & PG_MODE_PAE) {
uint64_t pde, pdpe;
target_ulong pdpe_addr;
#ifdef TARGET_X86_64
- if (env->nested_pg_mode & SVM_NPT_LMA) {
+ if (env->nested_pg_mode & PG_MODE_LMA) {
uint64_t pml5e;
uint64_t pml4e_addr, pml4e;
@@ -147,7 +165,7 @@ static hwaddr get_hphys(CPUState *cs, hwaddr gphys,
MMUAccessType access_type,
ptep = pde | PG_NX_MASK;
/* if host cr4 PSE bit is set, then we use a 4MB page */
- if ((pde & PG_PSE_MASK) && (env->nested_pg_mode & SVM_NPT_PSE)) {
+ if ((pde & PG_PSE_MASK) && (env->nested_pg_mode & PG_MODE_PSE)) {
page_size = 4096 * 1024;
pte_addr = pde_addr;
diff --git a/target/i386/tcg/sysemu/svm_helper.c
b/target/i386/tcg/sysemu/svm_helper.c
index d6c2cccda6..4d81d341b8 100644
--- a/target/i386/tcg/sysemu/svm_helper.c
+++ b/target/i386/tcg/sysemu/svm_helper.c
@@ -163,18 +163,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int
next_eip_addend)
control.nested_cr3));
env->hflags2 |= HF2_NPT_MASK;
- if (env->cr[4] & CR4_PAE_MASK) {
- env->nested_pg_mode |= SVM_NPT_PAE;
- }
- if (env->cr[4] & CR4_PSE_MASK) {
- env->nested_pg_mode |= SVM_NPT_PSE;
- }
- if (env->hflags & HF_LMA_MASK) {
- env->nested_pg_mode |= SVM_NPT_LMA;
- }
- if (env->efer & MSR_EFER_NXE) {
- env->nested_pg_mode |= SVM_NPT_NXE;
- }
+ env->nested_pg_mode = get_pg_mode(env);
}
/* enable intercepts */
--
2.26.2
- [PULL 01/33] target/i386: Rename helper_fldt, helper_fstt, (continued)
- [PULL 01/33] target/i386: Rename helper_fldt, helper_fstt, Paolo Bonzini, 2021/05/11
- [PULL 08/33] i386: split off sysemu-only functionality in tcg-cpu, Paolo Bonzini, 2021/05/11
- [PULL 03/33] i386: split cpu accelerators from cpu.c, using AccelCPUClass, Paolo Bonzini, 2021/05/11
- [PULL 09/33] i386: split smm helper (sysemu), Paolo Bonzini, 2021/05/11
- [PULL 07/33] accel-cpu: make cpu_realizefn return a bool, Paolo Bonzini, 2021/05/11
- [PULL 06/33] target/i386: fix host_cpu_adjust_phys_bits error handling, Paolo Bonzini, 2021/05/11
- [PULL 05/33] accel: introduce new accessor functions, Paolo Bonzini, 2021/05/11
- [PULL 18/33] target/i386: gdbstub: only write CR0/CR2/CR3/EFER for sysemu, Paolo Bonzini, 2021/05/11
- [PULL 19/33] i386: make cpu_load_efer sysemu-only, Paolo Bonzini, 2021/05/11
- [PULL 20/33] accel: move call to accel_init_interfaces, Paolo Bonzini, 2021/05/11
- [PULL 23/33] target/i386: move paging mode constants from SVM to cpu.h,
Paolo Bonzini <=
- [PULL 17/33] target/i386: gdbstub: introduce aux functions to read/write CS64 regs, Paolo Bonzini, 2021/05/11
- [PULL 14/33] i386: split svm_helper into sysemu and stub-only user, Paolo Bonzini, 2021/05/11
- [PULL 11/33] i386: move TCG bpt_helper into sysemu/, Paolo Bonzini, 2021/05/11
- [PULL 10/33] i386: split tcg excp_helper into sysemu and user parts, Paolo Bonzini, 2021/05/11
- [PULL 12/33] i386: split misc helper user stubs and sysemu part, Paolo Bonzini, 2021/05/11
- [PULL 15/33] i386: split seg_helper into user-only and sysemu parts, Paolo Bonzini, 2021/05/11
- [PULL 13/33] i386: separate fpu_helper sysemu-only parts, Paolo Bonzini, 2021/05/11
- [PULL 22/33] target/i386: merge SVM_NPTEXIT_* with PF_ERROR_* constants, Paolo Bonzini, 2021/05/11
- [PULL 32/33] configure: fix detection of gdbus-codegen, Paolo Bonzini, 2021/05/11
- [PULL 26/33] target/i386: extend pg_mode to more CR0 and CR4 bits, Paolo Bonzini, 2021/05/11