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[PULL 06/33] target/i386: fix host_cpu_adjust_phys_bits error handling
From: |
Paolo Bonzini |
Subject: |
[PULL 06/33] target/i386: fix host_cpu_adjust_phys_bits error handling |
Date: |
Tue, 11 May 2021 04:13:23 -0400 |
From: Claudio Fontana <cfontana@suse.de>
move the check for phys_bits outside of host_cpu_adjust_phys_bits,
because otherwise it is impossible to return an error condition
explicitly.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210322132800.7470-8-cfontana@suse.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/host-cpu.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/target/i386/host-cpu.c b/target/i386/host-cpu.c
index 9cfe56ce41..d07d41c34c 100644
--- a/target/i386/host-cpu.c
+++ b/target/i386/host-cpu.c
@@ -50,7 +50,7 @@ static void host_cpu_enable_cpu_pm(X86CPU *cpu)
env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
}
-static uint32_t host_cpu_adjust_phys_bits(X86CPU *cpu, Error **errp)
+static uint32_t host_cpu_adjust_phys_bits(X86CPU *cpu)
{
uint32_t host_phys_bits = host_cpu_phys_bits();
uint32_t phys_bits = cpu->phys_bits;
@@ -77,14 +77,6 @@ static uint32_t host_cpu_adjust_phys_bits(X86CPU *cpu, Error
**errp)
}
}
- if (phys_bits &&
- (phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
- phys_bits < 32)) {
- error_setg(errp, "phys-bits should be between 32 and %u "
- " (but is %u)",
- TARGET_PHYS_ADDR_SPACE_BITS, phys_bits);
- }
-
return phys_bits;
}
@@ -97,7 +89,17 @@ void host_cpu_realizefn(CPUState *cs, Error **errp)
host_cpu_enable_cpu_pm(cpu);
}
if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
- cpu->phys_bits = host_cpu_adjust_phys_bits(cpu, errp);
+ uint32_t phys_bits = host_cpu_adjust_phys_bits(cpu);
+
+ if (phys_bits &&
+ (phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
+ phys_bits < 32)) {
+ error_setg(errp, "phys-bits should be between 32 and %u "
+ " (but is %u)",
+ TARGET_PHYS_ADDR_SPACE_BITS, phys_bits);
+ return;
+ }
+ cpu->phys_bits = phys_bits;
}
}
--
2.26.2
- [PULL 00/33] Misc (mostly i386) patches for 2021-05-11, Paolo Bonzini, 2021/05/11
- [PULL 04/33] cpu: call AccelCPUClass::cpu_realizefn in cpu_exec_realizefn, Paolo Bonzini, 2021/05/11
- [PULL 02/33] target/i386: Split out do_fsave, do_frstor, do_fxsave, do_fxrstor, Paolo Bonzini, 2021/05/11
- [PULL 01/33] target/i386: Rename helper_fldt, helper_fstt, Paolo Bonzini, 2021/05/11
- [PULL 08/33] i386: split off sysemu-only functionality in tcg-cpu, Paolo Bonzini, 2021/05/11
- [PULL 03/33] i386: split cpu accelerators from cpu.c, using AccelCPUClass, Paolo Bonzini, 2021/05/11
- [PULL 09/33] i386: split smm helper (sysemu), Paolo Bonzini, 2021/05/11
- [PULL 07/33] accel-cpu: make cpu_realizefn return a bool, Paolo Bonzini, 2021/05/11
- [PULL 06/33] target/i386: fix host_cpu_adjust_phys_bits error handling,
Paolo Bonzini <=
- [PULL 05/33] accel: introduce new accessor functions, Paolo Bonzini, 2021/05/11
- [PULL 18/33] target/i386: gdbstub: only write CR0/CR2/CR3/EFER for sysemu, Paolo Bonzini, 2021/05/11
- [PULL 19/33] i386: make cpu_load_efer sysemu-only, Paolo Bonzini, 2021/05/11
- [PULL 20/33] accel: move call to accel_init_interfaces, Paolo Bonzini, 2021/05/11
- [PULL 23/33] target/i386: move paging mode constants from SVM to cpu.h, Paolo Bonzini, 2021/05/11
- [PULL 17/33] target/i386: gdbstub: introduce aux functions to read/write CS64 regs, Paolo Bonzini, 2021/05/11
- [PULL 14/33] i386: split svm_helper into sysemu and stub-only user, Paolo Bonzini, 2021/05/11
- [PULL 11/33] i386: move TCG bpt_helper into sysemu/, Paolo Bonzini, 2021/05/11
- [PULL 10/33] i386: split tcg excp_helper into sysemu and user parts, Paolo Bonzini, 2021/05/11
- [PULL 12/33] i386: split misc helper user stubs and sysemu part, Paolo Bonzini, 2021/05/11