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Re: [PULL 00/36] MIPS patches for 2021-05-02


From: Peter Maydell
Subject: Re: [PULL 00/36] MIPS patches for 2021-05-02
Date: Tue, 4 May 2021 10:09:52 +0100

On Sun, 2 May 2021 at 17:20, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> The following changes since commit 53c5433e84e8935abed8e91d4a2eb813168a0ecf:
>
>   Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210501' 
> into staging (2021-05-02 12:02:46 +0100)
>
> are available in the Git repository at:
>
>   https://github.com/philmd/qemu.git tags/mips-20210502
>
> for you to fetch changes up to 1c13514449439b5ff1f746ed0bf73b298da39cf0:
>
>   gitlab-ci: Add KVM mips64el cross-build jobs (2021-05-02 16:49:35 +0200)
>
> ----------------------------------------------------------------
> MIPS patches queue
>
> - Fix CACHEE opcode
> - Add missing CP0 checks to nanoMIPS RDPGPR / WRPGPR opcodes
> - Remove isa_get_irq() call in PIIX4 south bridge
> - Add various missing fields to the MIPS CPU migration vmstate
> - Lot of code moved around to allow TCG or KVM only builds
> - Restrict non-virtualized machines to TCG
> - Add KVM mips64el cross-build jobs to gitlab-ci
>
>
> scripts/checkpatch.pl false positive in patch 31
> "Move TLB management helpers to tcg/sysemu/tlb_helper.c":
>
> 4 checkpatch errors:
>
>   ERROR: space prohibited after that '&' (ctx:WxW)
>   #414: FILE: target/mips/tcg/sysemu/tlb_helper.c:71:
>   +    tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
>                                                     ^
>
>   ERROR: space prohibited after that '&' (ctx:WxW)
>   #415: FILE: target/mips/tcg/sysemu/tlb_helper.c:72:
>   +    tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
>                                                     ^
>
>   ERROR: space prohibited after that '&' (ctx:WxW)
>   #420: FILE: target/mips/tcg/sysemu/tlb_helper.c:77:
>   +    tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
>                                                     ^
>
>   ERROR: space prohibited after that '&' (ctx:WxW)
>   #421: FILE: target/mips/tcg/sysemu/tlb_helper.c:78:
>   +    tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
>                                                     ^
>
>   total: 4 errors, 0 warnings, 688 lines checked

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1
for any user-visible changes.

-- PMM



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