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[RFC PATCH v2 4/4] target/mips: Allow using the 34Kf with 16/32/64 prese
From: |
Philippe Mathieu-Daudé |
Subject: |
[RFC PATCH v2 4/4] target/mips: Allow using the 34Kf with 16/32/64 preset TLB entries |
Date: |
Fri, 16 Oct 2020 00:47:46 +0200 |
Per "MIPS32 34K Processor Core Family Software User's Manual,
Revision 01.13" page 8 in "Joint TLB (JTLB)" section:
"The JTLB is a fully associative TLB cache containing 16, 32,
or 64-dual-entries mapping up to 128 virtual pages to their
corresponding physical addresses."
Add these values to the CP0_Config1_MMU_preset array.
Example to use a 34Kf cpu with preset 64 TLB:
$ qemu-system-mipsel -cpu 34Kf,tlb-entries=64 ...
This is helpful for developers of the Yocto Project [*]:
Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit
MIPS CI loop. It was observed that in this case CI test execution
time was almost twice longer than 64bit MIPS variant that runs
under MIPS64R2-generic model. It was investigated and concluded
that the difference in number of TLBs 16 in 34Kf case vs 64 in
MIPS64R2-generic is responsible for most of CI real time execution
difference. Because with 16 TLBs linux user-land trashes TLB more
and it needs to execute more instructions in TLB refill handler
calls, as result it runs much longer.
[*] https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html
Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992
Reported-by: Victor Kamensky <kamensky@cisco.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate_init.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index a426463c434..02500e696f4 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -258,6 +258,7 @@ const mips_def_t mips_defs[] =
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
(1 << CP0C1_CA),
+ .CP0_Config1_MMU_preset = (const unsigned[]){16, 32, 64, 0},
.CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
(1 << CP0C3_DSPP),
--
2.26.2