RE: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU

[Jiangyifei]

> -----Original Message-----
> From: Alistair Francis [mailto:alistair23@gmail.com]
> Sent: Thursday, October 15, 2020 3:12 AM
> To: Richard Henderson <richard.henderson@linaro.org>
> Cc: Jiangyifei <jiangyifei@huawei.com>; qemu-devel@nongnu.org;
> qemu-riscv@nongnu.org; Zhanghailiang <zhang.zhanghailiang@huawei.com>;
> sagark@eecs.berkeley.edu; kbastian@mail.uni-paderborn.de; Zhangxiaofeng
> (F) <victor.zhangxiaofeng@huawei.com>; Alistair.Francis@wdc.com; yinyipeng
> <yinyipeng1@huawei.com>; palmer@dabbelt.com; Wubin (H)
> <wu.wubin@huawei.com>; dengkai (A) <dengkai1@huawei.com>
> Subject: Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
> 
> On Wed, Oct 14, 2020 at 8:45 AM Richard Henderson
> <richard.henderson@linaro.org> wrote:
> >
> > On 10/14/20 3:21 AM, Jiangyifei wrote:
> > >> Would this be a good time to expand mstatus to uint64_t instead of
> > >> target_ulong so that it can be saved as one unit and reduce some
> > >> ifdefs in the code base?
> > >>
> > >> Similarly with some of the other status registers that are two
> > >> halved for riscv32.
> > >
> > > I agree with you that it should be rearranged.
> > > But I hope this series will focus on achieving migration.
> > > Can I send another patch to rearrange it later?
> >
> > Well, that changes the bit layout for migration.
> > While we could bump the version number, it seemed easier to change the
> > representation first.
> 
> +1 it would be great to consolidate these.
> 
> Alistair
> 

OK. I will change this in the next series.

Yifei

> >
> >
> > r~
> >