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Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU |
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Date: |
Wed, 14 Oct 2020 12:12:23 -0700 |
On Wed, Oct 14, 2020 at 8:45 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 10/14/20 3:21 AM, Jiangyifei wrote:
> >> Would this be a good time to expand mstatus to uint64_t instead of
> >> target_ulong so that it can be saved as one unit and reduce some ifdefs in
> >> the
> >> code base?
> >>
> >> Similarly with some of the other status registers that are two halved for
> >> riscv32.
> >
> > I agree with you that it should be rearranged.
> > But I hope this series will focus on achieving migration.
> > Can I send another patch to rearrange it later?
>
> Well, that changes the bit layout for migration.
> While we could bump the version number, it seemed
> easier to change the representation first.
+1 it would be great to consolidate these.
Alistair
>
>
> r~
>
[PATCH V2 4/5] target/riscv: Add V extension state description, Yifei Jiang, 2020/10/10
[PATCH V2 3/5] target/riscv: Add H extension state description, Yifei Jiang, 2020/10/10
[PATCH V2 5/5] target/riscv: Add sifive_plic vmstate, Yifei Jiang, 2020/10/10
[PATCH V2 2/5] target/riscv: Add PMP state description, Yifei Jiang, 2020/10/10