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From: | Richard Henderson |
Subject: | Re: [RFC v4 38/70] target/riscv: rvv-1.0: whole register move instructions |
Date: | Sat, 29 Aug 2020 13:08:51 -0700 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 8/17/20 1:49 AM, frank.chang@sifive.com wrote: > From: Frank Chang <frank.chang@sifive.com> > > Add the following instructions: > > * vmv1r.v > * vmv2r.v > * vmv4r.v > * vmv8r.v > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > --- > target/riscv/insn32.decode | 4 ++++ > target/riscv/insn_trans/trans_rvv.inc.c | 25 +++++++++++++++++++++++++ > 2 files changed, 29 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
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