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Re: [RFC v4 00/70] support vector extension v1.0
From: |
Alistair Francis |
Subject: |
Re: [RFC v4 00/70] support vector extension v1.0 |
Date: |
Wed, 26 Aug 2020 09:45:22 -0700 |
On Tue, Aug 25, 2020 at 1:29 AM Frank Chang <frank.chang@sifive.com> wrote:
>
> On Mon, Aug 17, 2020 at 4:50 PM <frank.chang@sifive.com> wrote:
>>
>> From: Frank Chang <frank.chang@sifive.com>
>>
>> This patchset implements the vector extension v1.0 for RISC-V on QEMU.
>>
>> This patchset is sent as RFC because RVV v1.0 is still in draft state.
>> v2 patchset was sent for RVV v0.9 and bumped to RVV v1.0 since v3 patchset.
>>
>> The port is available here:
>> https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v4
>>
>> You can change the cpu argument: vext_spec to v1.0 (i.e. vext_spec=v1.0)
>> to run with RVV v1.0 instructions.
>>
>> Note: This patchset depends on two other patchsets listed in Based-on
>> section below so it might not able to be built unless those two
>> patchsets are applied.
>>
>> Changelog:
>>
>> v4
>> * remove explicit float flmul variable in DisasContext.
>> * replace floating-point calculations with shift operations to
>> improve performance.
>> * relax RV_VLEN_MAX to 512-bits.
>>
>> v3
>> * apply nan-box helpers from Richard Henderson.
>> * remove fp16 api changes as they are sent independently in another
>> pathcset by Chih-Min Chao.
>> * remove all tail elements clear functions as tail elements can
>> retain unchanged for either VTA set to undisturbed or agnostic.
>> * add fp16 nan-box check generator function.
>> * add floating-point rounding mode enum.
>> * replace flmul arithmetic with shifts to avoid floating-point
>> conversions.
>> * add Zvqmac extension.
>> * replace gdbstub vector register xml files with dynamic generator.
>> * bumped to RVV v1.0.
>> * RVV v1.0 related changes:
>> * add vl<nf>re<eew>.v and vs<nf>r.v vector whole register
>> load/store instructions
>> * add vrgatherei16 instruction.
>> * rearranged bits in vtype to make vlmul bits into a contiguous
>> field.
>>
>> v2
>> * drop v0.7.1 support.
>> * replace invisible return check macros with functions.
>> * move mark_vs_dirty() to translators.
>> * add SSTATUS_VS flag for s-mode.
>> * nan-box scalar fp register for floating-point operations.
>> * add gdbstub files for vector registers to allow system-mode
>> debugging with GDB.
>>
>> Based-on: <20200724002807.441147-1-richard.henderson@linaro.org/>
>> Based-on: <1596102747-20226-1-git-send-email-chihmin.chao@sifive.com/>
>>
>> Frank Chang (62):
>> target/riscv: drop vector 0.7.1 and add 1.0 support
>> target/riscv: Use FIELD_EX32() to extract wd field
>> target/riscv: rvv-1.0: introduce writable misa.v field
>> target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
>> target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr
>> registers
>> target/riscv: rvv-1.0: remove MLEN calculations
>> target/riscv: rvv-1.0: add fractional LMUL
>> target/riscv: rvv-1.0: add VMA and VTA
>> target/riscv: rvv-1.0: update check functions
>> target/riscv: introduce more imm value modes in translator functions
>> target/riscv: rvv:1.0: add translation-time nan-box helper function
>> target/riscv: rvv-1.0: configure instructions
>> target/riscv: rvv-1.0: stride load and store instructions
>> target/riscv: rvv-1.0: index load and store instructions
>> target/riscv: rvv-1.0: fix address index overflow bug of indexed
>> load/store insns
>> target/riscv: rvv-1.0: fault-only-first unit stride load
>> target/riscv: rvv-1.0: amo operations
>> target/riscv: rvv-1.0: load/store whole register instructions
>> target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
>> target/riscv: rvv-1.0: take fractional LMUL into vector max elements
>> calculation
>> target/riscv: rvv-1.0: floating-point square-root instruction
>> target/riscv: rvv-1.0: floating-point classify instructions
>> target/riscv: rvv-1.0: mask population count instruction
>> target/riscv: rvv-1.0: find-first-set mask bit instruction
>> target/riscv: rvv-1.0: set-X-first mask bit instructions
>> target/riscv: rvv-1.0: iota instruction
>> target/riscv: rvv-1.0: element index instruction
>> target/riscv: rvv-1.0: allow load element with sign-extended
>> target/riscv: rvv-1.0: register gather instructions
>> target/riscv: rvv-1.0: integer scalar move instructions
>> target/riscv: rvv-1.0: floating-point move instruction
>> target/riscv: rvv-1.0: floating-point scalar move instructions
>> target/riscv: rvv-1.0: whole register move instructions
>> target/riscv: rvv-1.0: integer extension instructions
>> target/riscv: rvv-1.0: single-width averaging add and subtract
>> instructions
>> target/riscv: rvv-1.0: single-width bit shift instructions
>> target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
>> target/riscv: rvv-1.0: narrowing integer right shift instructions
>> target/riscv: rvv-1.0: widening integer multiply-add instructions
>> target/riscv: rvv-1.0: add Zvqmac extension
>> target/riscv: rvv-1.0: quad-widening integer multiply-add instructions
>> target/riscv: rvv-1.0: single-width saturating add and subtract
>> instructions
>> target/riscv: rvv-1.0: integer comparison instructions
>> target/riscv: use softfloat lib float16 comparison functions
>> target/riscv: rvv-1.0: floating-point compare instructions
>> target/riscv: rvv-1.0: mask-register logical instructions
>> target/riscv: rvv-1.0: slide instructions
>> target/riscv: rvv-1.0: floating-point slide instructions
>> target/riscv: rvv-1.0: narrowing fixed-point clip instructions
>> target/riscv: rvv-1.0: single-width floating-point reduction
>> target/riscv: rvv-1.0: widening floating-point reduction instructions
>> target/riscv: rvv-1.0: single-width scaling shift instructions
>> target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
>> target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
>> target/riscv: rvv-1.0: remove integer extract instruction
>> target/riscv: rvv-1.0: floating-point min/max instructions
>> target/riscv: introduce floating-point rounding mode enum
>> target/riscv: rvv-1.0: floating-point/integer type-convert
>> instructions
>> target/riscv: rvv-1.0: widening floating-point/integer type-convert
>> target/riscv: add "set round to odd" rounding mode helper function
>> target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
>> target/riscv: rvv-1.0: relax RV_VLEN_MAX to 512-bits
>>
>> Greentime Hu (2):
>> target/riscv: rvv-1.0: add vlenb register
>> target/riscv: gdb: support vector registers for rv32
>>
>> Hsiangkai Wang (2):
>> target/riscv: gdb: modify gdb csr xml file to align with csr register
>> map
>> target/riscv: gdb: support vector registers for rv64
>>
>> LIU Zhiwei (4):
>> target/riscv: rvv-1.0: add mstatus VS field
>> target/riscv: rvv-1.0: add sstatus VS field
>> target/riscv: rvv-1.0: add translation-time vector context status
>> target/riscv: rvv-1.0: add vcsr register
>>
>> gdb-xml/riscv-32bit-csr.xml | 18 +-
>> gdb-xml/riscv-64bit-csr.xml | 18 +-
>> target/riscv/cpu.c | 12 +-
>> target/riscv/cpu.h | 97 +-
>> target/riscv/cpu_bits.h | 10 +
>> target/riscv/cpu_helper.c | 16 +-
>> target/riscv/csr.c | 73 +-
>> target/riscv/fpu_helper.c | 17 +-
>> target/riscv/gdbstub.c | 126 +-
>> target/riscv/helper.h | 523 ++--
>> target/riscv/insn32-64.decode | 18 +-
>> target/riscv/insn32.decode | 295 +-
>> target/riscv/insn_trans/trans_rvv.inc.c | 2366 ++++++++++------
>> target/riscv/internals.h | 19 +-
>> target/riscv/translate.c | 68 +-
>> target/riscv/vector_helper.c | 3269 +++++++++++------------
>> 16 files changed, 4051 insertions(+), 2894 deletions(-)
>>
>> --
>> 2.17.1
>>
>
> ping~
I wasn't really following too closely, but didn't Richard give comments?
Alistair
- [RFC v4 62/70] target/riscv: introduce floating-point rounding mode enum, (continued)
- [RFC v4 62/70] target/riscv: introduce floating-point rounding mode enum, frank . chang, 2020/08/17
- [RFC v4 63/70] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2020/08/17
- [RFC v4 64/70] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2020/08/17
- [RFC v4 65/70] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2020/08/17
- [RFC v4 66/70] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2020/08/17
- [RFC v4 67/70] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 512-bits, frank . chang, 2020/08/17
- [RFC v4 68/70] target/riscv: gdb: modify gdb csr xml file to align with csr register map, frank . chang, 2020/08/17
- [RFC v4 69/70] target/riscv: gdb: support vector registers for rv64, frank . chang, 2020/08/17
- [RFC v4 70/70] target/riscv: gdb: support vector registers for rv32, frank . chang, 2020/08/17
- Re: [RFC v4 00/70] support vector extension v1.0, Frank Chang, 2020/08/25
- Re: [RFC v4 00/70] support vector extension v1.0,
Alistair Francis <=