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Re: [PATCH 03/21] softfloat: add xtensa specialization for pickNaNMulAdd
From: |
Richard Henderson |
Subject: |
Re: [PATCH 03/21] softfloat: add xtensa specialization for pickNaNMulAdd |
Date: |
Wed, 8 Jul 2020 09:07:39 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 |
On 7/6/20 4:47 PM, Max Filippov wrote:
> pickNaNMulAdd logic on Xtensa is the same as pickNaN when applied to
> the expression (a * b) + c. So with two pickNaN variants there must be
> two pickNaNMulAdd variants.
"Is the same as"?
I question the non-use of the infzero parameter.
When infzero, (a * b) = (Inf * 0), which will produce a default QNaN. Your
sentence above would suggest that pickNaN is applied twice, so that if
use_first_nan, the default nan is chosen above any nan within c.
In addition, is the invalid flag raised for (Inf * 0) + NaN? Does that happen
regardless of the use_first_nan setting, or does the whole operation
short-circuit?
r~
- [PATCH 00/21] target/xtensa: implement double precision FPU, Max Filippov, 2020/07/06
- [PATCH 02/21] softfloat: pass float_status pointer to pickNaN, Max Filippov, 2020/07/06
- [PATCH 01/21] softfloat: make NO_SIGNALING_NANS runtime property, Max Filippov, 2020/07/06
- [PATCH 03/21] softfloat: add xtensa specialization for pickNaNMulAdd, Max Filippov, 2020/07/06
- [PATCH 04/21] target/xtensa: add geometry to xtensa_get_regfile_by_name, Max Filippov, 2020/07/06
- [PATCH 06/21] target/xtensa: rename FPU2000 translators and helpers, Max Filippov, 2020/07/06
- [PATCH 07/21] target/xtensa: move FSR/FCR register accessors, Max Filippov, 2020/07/06
- [PATCH 05/21] target/xtensa: support copying registers up to 64 bits wide, Max Filippov, 2020/07/06
- [PATCH 08/21] target/xtensa: don't access BR regfile directly, Max Filippov, 2020/07/06