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[PULL v2 59/64] target/riscv: integer scalar move instruction
From: |
Alistair Francis |
Subject: |
[PULL v2 59/64] target/riscv: integer scalar move instruction |
Date: |
Thu, 2 Jul 2020 09:23:49 -0700 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-57-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/internals.h | 6 +++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 60 +++++++++++++++++++++++++
3 files changed, 67 insertions(+)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index f3cea478f7..37d33820ad 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -32,4 +32,10 @@ FIELD(VDATA, WD, 11, 1)
target_ulong fclass_h(uint64_t frs1);
target_ulong fclass_s(uint64_t frs1);
target_ulong fclass_d(uint64_t frs1);
+
+#define SEW8 0
+#define SEW16 1
+#define SEW32 2
+#define SEW64 3
+
#endif
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c4496cd010..e06c0ffc22 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -564,6 +564,7 @@ vmsof_m 010110 . ..... 00010 010 ..... 1010111
@r2_vm
viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
+vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index cfbbd88dbf..b10b89daa9 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2649,3 +2649,63 @@ static bool trans_vext_x_v(DisasContext *s, arg_r *a)
tcg_temp_free_i64(tmp);
return true;
}
+
+/* Integer Scalar Move Instruction */
+
+static void store_element(TCGv_i64 val, TCGv_ptr base,
+ int ofs, int sew)
+{
+ switch (sew) {
+ case MO_8:
+ tcg_gen_st8_i64(val, base, ofs);
+ break;
+ case MO_16:
+ tcg_gen_st16_i64(val, base, ofs);
+ break;
+ case MO_32:
+ tcg_gen_st32_i64(val, base, ofs);
+ break;
+ case MO_64:
+ tcg_gen_st_i64(val, base, ofs);
+ break;
+ default:
+ g_assert_not_reached();
+ break;
+ }
+}
+
+/*
+ * Store vreg[idx] = val.
+ * The index must be in range of VLMAX.
+ */
+static void vec_element_storei(DisasContext *s, int vreg,
+ int idx, TCGv_i64 val)
+{
+ store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew);
+}
+
+/* vmv.s.x vd, rs1 # vd[0] = rs1 */
+static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
+{
+ if (vext_check_isa_ill(s)) {
+ /* This instruction ignores LMUL and vector register groups */
+ int maxsz = s->vlen >> 3;
+ TCGv_i64 t1;
+ TCGLabel *over = gen_new_label();
+
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0);
+ if (a->rs1 == 0) {
+ goto done;
+ }
+
+ t1 = tcg_temp_new_i64();
+ tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
+ vec_element_storei(s, a->rd, 0, t1);
+ tcg_temp_free_i64(t1);
+ done:
+ gen_set_label(over);
+ return true;
+ }
+ return false;
+}
--
2.27.0
- [PULL v2 50/64] target/riscv: vector single-width floating-point reduction instructions, (continued)
- [PULL v2 50/64] target/riscv: vector single-width floating-point reduction instructions, Alistair Francis, 2020/07/02
- [PULL v2 49/64] target/riscv: vector wideing integer reduction instructions, Alistair Francis, 2020/07/02
- [PULL v2 51/64] target/riscv: vector widening floating-point reduction instructions, Alistair Francis, 2020/07/02
- [PULL v2 52/64] target/riscv: vector mask-register logical instructions, Alistair Francis, 2020/07/02
- [PULL v2 53/64] target/riscv: vector mask population count vmpopc, Alistair Francis, 2020/07/02
- [PULL v2 56/64] target/riscv: vector iota instruction, Alistair Francis, 2020/07/02
- [PULL v2 55/64] target/riscv: set-X-first mask bit, Alistair Francis, 2020/07/02
- [PULL v2 54/64] target/riscv: vmfirst find-first-set mask bit, Alistair Francis, 2020/07/02
- [PULL v2 57/64] target/riscv: vector element index instruction, Alistair Francis, 2020/07/02
- [PULL v2 58/64] target/riscv: integer extract instruction, Alistair Francis, 2020/07/02
- [PULL v2 59/64] target/riscv: integer scalar move instruction,
Alistair Francis <=
- [PULL v2 60/64] target/riscv: floating-point scalar move instructions, Alistair Francis, 2020/07/02
- [PULL v2 61/64] target/riscv: vector slide instructions, Alistair Francis, 2020/07/02
- [PULL v2 64/64] target/riscv: configure and turn on vector extension from command line, Alistair Francis, 2020/07/02
- [PULL v2 62/64] target/riscv: vector register gather instruction, Alistair Francis, 2020/07/02
- [PULL v2 63/64] target/riscv: vector compress instruction, Alistair Francis, 2020/07/02
- Re: [PULL v2 00/64] riscv-to-apply queue, no-reply, 2020/07/02
- Re: [PULL v2 00/64] riscv-to-apply queue, Peter Maydell, 2020/07/03